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...vial tests available that have been known to cause problems with channel recovery in the past let me know and I'll start testing those as well. Alistair Popple (5): drm/nouveau: Fix MMU fault interrupts on Turing drm/nouveau: Remove Turing interrupt hack drm/nouveau: Move Turing specific FIFO functions drm/nouveau: FIFO interrupt fixes for Turing drm/nouveau: Turing channel preemption fix .../gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 46 +-- .../gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 32 ++ .../gpu/drm/nouveau/nvkm/engine/fifo/tu102.c | 364 +++++++++++++++++- .../gpu/dr...

From: Thierry Reding <treding at nvidia.com> The purpose of BAR1 is primarily to make memory accesses coherent. However, some GPUs do not have BAR1 functionality. For example, the GV11B found on the Xavier SoC is DMA coherent and therefore doesn't need BAR1. Implement a variant of FIFO channels that work without a mapping of instance memory through BAR1. XXX ensure memory barriers are in place for writes Signed-off-by: Thierry Reding <treding at nvidia.com> --- Hi Ben, I'm sending this a bit out of context (it's part of the larger series to enable basic GV11B sup...

Hi, I am having issues with nouveau driver in 4.11 Debian distribution kernel. I can start X session but the screen locks up e.g. when I try to exit mplayer fullscreen mode. The lock is swamped with tons of nouveau 0000:03:00.0: fifo: SCHED_ERROR 13 [] messages and I also can see some warnings ------------[ cut here ]------------ WARNING: CPU: 1 PID: 3535 at /build/linux-J4LMtv/linux-4.11.6/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c:85 gf100_fifo_gpfifo_engine_fini+0x14f/0x1d0 [nouveau] nouveau 0000:03:00.0: tim...

...guest doamin via "virsh create abcd.xml" i see an additional libvirt thread and also some open files: pstree -h `pgrep libvirtd` libvirtd───11*[{libvirtd}] libvirtd 3016 root 21w REG 253,0 6044 1052094 /var/log/libvirt/libxl/abcd.log libvirtd 3016 root 22r FIFO 0,8 0t0 126124 pipe libvirtd 3016 root 23w FIFO 0,8 0t0 126124 pipe libvirtd 3016 root 24u REG 0,37 0 4 /proc/xen/privcmd libvirtd 3016 root 25u unix 0xffff8807d2c3ad80 0t0 126125 socket libvirtd 3016...

...te[21117]] [ 1713.441260] nouveau 0000:01:00.0: gr: GPC0/TPC0/MP trap: global 00000004 [MULTIPLE_WARP_ERRORS] warp 20005 [MISALIGNED_PC] [ 1713.441265] nouveau 0000:01:00.0: gr: GPC0/TPC1/MP trap: global 00000004 [MULTIPLE_WARP_ERRORS] warp 20005 [MISALIGNED_PC] [ 1717.773839] nouveau 0000:01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT] [ 1717.773848] nouveau 0000:01:00.0: fifo: sw engine fault on channel 2, recovering... [ 1719.776529] nouveau 0000:01:00.0: fifo: runlist 0 update timeout [ 1722.068923] nouveau 0000:01:00.0: fifo: SCHED_ERROR 0a [CTXSW_TIMEOUT] [ 1726.363660] nouveau 0000:01:00.0: f...

On Sat, Feb 01, 2014 at 12:16:54PM +0900, Alexandre Courbot wrote: > GK20A's FIFO is compatible with NVE0, but only features 128 channels and > 1 runlist. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > drivers/gpu/drm/nouveau/Makefile | 1 + > drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h | 1 + > drive...

Friends I need to get R reading from a fifo. I want it to block till there is some data in the fifo, consume what input it gets there, do some thing with it then loop back and block again. Very simple. Yes? No. The example in the documentation works OK.. zz <- fifo("foo-fifo", "w+") writeLines("...

...nux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>): drivers/platform/mellanox/mlxbf-tmfifo.c: In function 'mlxbf_tmfifo_probe': >> drivers/platform/mellanox/mlxbf-tmfifo.c:1237:2: error: invalid preprocessing directive #defined; did you mean #define? 1237 | #defined MLXBF_TMFIFO_LITTLE_ENDIAN (virtio_legacy_is_little_endian() || | ^~~~~~~ | define...

...nux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp at intel.com> All errors (new ones prefixed by >>): drivers/platform/mellanox/mlxbf-tmfifo.c: In function 'mlxbf_tmfifo_probe': drivers/platform/mellanox/mlxbf-tmfifo.c:1237:70: warning: value computed is not used [-Wunused-value] 1237 | #define MLXBF_TMFIFO_LITTLE_ENDIAN (virtio_legacy_is_little_endian() || \ | ~~~~~~~~~~~~~~~~...

GK20A's FIFO is compatible with NVE0, but only features 128 channels and 1 runlist. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h | 1 + drivers/gpu/drm/nouveau/core/engine/fifo...

...tc). This just exposes the multiplier to userspace so the fence code gets things right, however I think this might all need more thought. Link: https://gitlab.freedesktop.org/drm/nouveau/-/issues/274 Signed-off-by: Dave Airlie <airlied at redhat.com> --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 7 ++++++- drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 2 ++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c | 7 +++++++ 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c i...

https://bugs.freedesktop.org/show_bug.cgi?id=103721 Bug ID: 103721 Summary: Frequent freezes with nouveau on Thinkpad P50 Product: xorg Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assignee: nouveau at

GK20A's FIFO is compatible with NVE0, but only features 128 channels and 1 runlist. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drivers/gpu/drm/nouveau/Makefile | 1 + drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h | 1 + drivers/gpu/drm/nouveau/core/engine/fifo...

The offset should be 8 on Kepler and later. Signed-off-by: Vince Hsu <vinceh at nvidia.com> --- drm/nouveau/nvkm/engine/fifo/gk104.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Hi, According to the header[1] the offset for engine status register is 8. [1] https://github.com/kfractal/nouveau/blob/hwref/drm/nouveau/include/nvkm/hwref/gk104/fifo.h Thanks, Vince diff --git a/drm/nouveau/nvkm/engine/fifo/gk104....

gcc with W=1 reports drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c:451:1: error: no previous prototype for ?gf100_fifo_nonstall_block? [-Werror=missing-prototypes] 451 | gf100_fifo_nonstall_block(struct nvkm_event *event, int type, int index) | ^~~~~~~~~~~~~~~~~~~~~~~~~ gf100_fifo_nonstall_block is only used in gf100.c, so it should be static S...

Bits 28:29 of RUNLIST_BASE specify the memory target of the runlist. Set it to 0x3 (SYS_MEM_NONCOHERENT) if the runlist object resides in system memory. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/engine/fifo/gf100.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/engine/fifo/gf100.c b/drm/nouveau/nvkm/engine/fifo/gf100.c index 36a39c7fd8d2..3cac5ebd0a4b 100644 --- a/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -54,6 +54,7 @...

In https://nouveau.freedesktop.org/KernelModuleParameters.html, there is: Here is a list of engines: DEVICE DMAOBJ PBSP PCE0 PCE1 PCE2 PCRYPT PDISP PFIFO PGRAPH PMPEG PPM PPPP PVP SW Also, in debug: CLIENT I have tried to find a description of those. https://envytools.readthedocs.io/en/latest/ help a bit, but I don't find a precise correlation. https://nouveau.freedesktop.org/NouveauTerms.html does not seems to have...

The following core dumps R 3.2.5, R 3.3.0 RC and R devel on Windows. I have tried to use a minimal setup (for all versions tested), i.e. C:\> cd C:\ C:\> set PATH=C:\PROGRA~1\R\R-33~1.0RC\bin C:\> set R_DEFAULT_PACKAGES=base C:\> R --quiet --vanilla > close(fifo("foo.tmp", open="wb")) [core dump] C:\> R --quiet --vanilla > con <- fifo('foo.tmp', open='wb') > print(con) description class mode text opened can read "\v" "fifo" "wb"...

...04, Paul Dufresne <dufresnep at zoho.com> wrote: > > In https://nouveau.freedesktop.org/KernelModuleParameters.html, there is: > Here is a list of engines: > DEVICE > DMAOBJ > PBSP > PCE0 > PCE1 > PCE2 > PCRYPT > PDISP > PFIFO > PGRAPH > PMPEG > PPM > PPPP > PVP > SW > Also, in debug: > CLIENT > > I have tried to find a description of those. > https://envytools.readthedocs.io/en/latest/ > help a bit, but I don't find a precise correlation. > > https...

...which means that one of the function pointers had been nulled out. Not sure if a race there would explain it, but maybe. There is also questionable ramht usage in channv50 and various disp code. If you think this is a good idea, those should probably be fixed up as well. drm/nouveau/nvkm/engine/fifo/dmanv04.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drm/nouveau/nvkm/engine/fifo/dmanv04.c index edec30f..0a7b6ed 100644 --- a/drm/nouveau/nvkm/engine/fifo/dmanv04.c +++ b/drm/nouveau/nvkm/engine/fifo/dmanv04.c @@ -37,7 +37,10 @@ nv04_fifo_dma_o...