Displaying 3 results from an estimated 3 matches for "ourtarget".
Did you mean:
yourtarget
2017 Mar 22
2
Building LLVM on Linux, executing on Windows 10 Linux Subsystem
...ot; \
"-DCMAKE_INSTALL_PREFIX:STRING=$(CLANG_INSTALL_ROOT)/Debug" \
"-DCMAKE_EXE_EXPORTS_C_FLAG:STRING=" \
"-DCMAKE_EXE_EXPORTS_CXX_FLAG:STRING=" \
"-DCMAKE_EXE_LINKER_FLAGS:STRING=-static-libgcc -static-libstdc++ -static" \
-DLLVM_TARGETS_TO_BUILD="OURTARGET" \
-DLLVM_DEFAULT_TARGET_TRIPLE=ourtarget
Only the highlighted options are perhaps unusual as I need to build with
statically linked GCC libraries, and the 'DCMAKE_EXE_EXPORTS' flags were
required to prevent another problem with dynamic libraries, though I have
forgotten what this...
2011 Jan 25
1
[LLVMdev] Trouble with virtual registers
...have indirect adressing. Should we be
creating a physical register directly somehow, or can we perhaps signal to
the allocator that the basic block's contents are updated?
Below is our storeRegToStackSlot, the ADDri instruction is transformed into
a copy-add pair in eliminateFrameIndex.
void OurTargetInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int
FrameIdx,
const TargetRegisterClass *RC,...
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...e, MVT::i40,
/* 30*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
MVT::i40, 0/*#Ops*/, // Results = #2
/* 36*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
MVT::i32, 0/*#Ops*/, // Results = #3
/* 42*/ OPC_EmitInteger, MVT::i32, OurTarget::hi16, // Results = #4
/* 45*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
MVT::i32, 3/*#Ops*/, 3, 0, 4, // Results = #5
/* 54*/ OPC_EmitNode1, TARGET_VAL(OurTarget::clearLo32_pseudo), 0,
MVT::i32, 1/*#Ops*/, 5, // Results = #6
/* 61*/ OP...