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I want to write a simple backend-specific instrinsic that will just call an instruction. How should I do that? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180924/7faeeb3d/attachment.html>

Hi, I am having issues running a new backend that I created for a new architecture. I suspect these errors may have something to do with how I have the string setup in LLVMTargetMachine() below? Also - It would be great if someone could point me to a document that describes some of these error messages? For example what does t26 ..t4 mean? Thanks in advance for taking your valuable time to help

...are not that hard to track down: compile the > failing testcase with -debug-only=isel and you'll see all the steps being > taken up to the moment of failure. The last few messages will be something > like "match failed at nnn". In your build directory in > lib/Target/<yourtarget> there will be a file <yourtarget>GenDAGISel.inc. > It contains the matching "script". The numbers nnn are shown in comments > in that file and correspond to the steps the matcher performs. You'll be > able to see what exactly it's trying to match. > > -Kr...

...: > It seems like d0 is always 14! > I check it with ARMGenAsmMatcher.inc it was the same! > How is it possible? because it should give the same register value that > matches the underlying platform not any autogenerated value!? The returned number is the register id as defined in <YourTarget>GenRegisterInfo.inc. These numbers don't have any meaning other than to represent a particular register. The 0x01 would be the encoding used in generating the binary. The D0 has id 14 on ARM because there are 13 other registers preceding it: namespace ARM { enum { NoRegister, APSR...

Dear all, in my TestRegisterInfo.td file, I defined a register like this: class TestReg<bits<6> enc, string name> : Register<name> { let HWEncoding{5-0} = enc; let Namespace = "TEST"; } def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>; but when I compile, the result I have in TestGenAsmMatcher.inc is this: case 'd': // 7

...not the > integer register set explicitly. I thought that aliases are transitive? > Or do I have to mention all aliases explicitly, e.g. for %d0 I need to > say [%s0,%s1,%GR0,%GR1]? Depending on how you defined the aliases, they aren't necessarily transitive. I'd like at the <yourtarget>GenRegisterInfo.inc file, and see what it lists as the aliases for each reg. > But a more interesting question is this: The scheme above assumes that > there is a "hardwired" mapping between FP registers and concerete pairs > of integer registers. In many cases this is eno...

...WARF APIs with gtest. [r289010](http://reviews.llvm.org/rL289010). * The SelectionDAG learned to expand `[US]MUL_LOHI`. Previously, setting it to expand would just prevent the node from being generated. [r289050](http://reviews.llvm.org/rL289050). * Tests written in .mir should go in test/CodeGen/YourTarget rather than test/CodeGen/MIR (that folder just contains tests for the MIR infrastructure). [r289254](http://reviews.llvm.org/rL289254). * The verifier learned to check TBAA metadata. [r289402](http://reviews.llvm.org/rL289402). ## Clang commits * Clang gained support for non-zero null pointers i...

Hi everyone, In response to yet-another fix in CodeGen affecting only an out-of-tree target (r231186), our lack of the ability to properly unit test CodeGen components has been highlighted. It was suggested that improving this situation might be a good GSoC project, and I agree, provided that we can settle on the scope and basic design ahead of time. I'd like to add that I feel this is a

...xplicitly. I thought that aliases are > transitive? > > Or do I have to mention all aliases explicitly, e.g. for %d0 I need > to > > say [%s0,%s1,%GR0,%GR1]? > > Depending on how you defined the aliases, they aren't necessarily > transitive. I'd like at the <yourtarget>GenRegisterInfo.inc file, > and see > what it lists as the aliases for each reg. Done. And I looked into the tblgen code. Tarnsitivity is not ensured by tblgen in any form, since it does not compute it. What it ensures is the commutativity of aliases, i.e. if A aliases B, then B aliases...

Hi, >> My target supports only f64 at the moment. >> Question: How can I tell LLVM that float is the same as double on my >> target? May be by assigning the same register class to both MVT::f32 ?> and MVT::f64? >Just don't assign a register class for the f32 type. This is what the >X86 backend does when it is in "floating point stack mode". This will

...calling convention representation. This will let you define stuff like: void foo() __attribute__(((mycall))) { } You can then use a #define to hide the attribute syntax. >> Depending on how you defined the aliases, they aren't necessarily >> transitive. I'd like at the <yourtarget>GenRegisterInfo.inc file, >> and see >> what it lists as the aliases for each reg. > > Done. And I looked into the tblgen code. Tarnsitivity is not ensured by > tblgen in any form, since it does not compute it. What it ensures is > the commutativity of aliases, i.e. if A...

On Mar 4, 2014, at 10:05 AM, Pete Cooper <peter_cooper at apple.com> wrote: > > On Mar 3, 2014, at 2:21 PM, Andrew Trick <atrick at apple.com> wrote: > >> >> On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: >> >>> Hi Andrew, >>> >>> We are currently using a custom model where