search for: opnodes

...cat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set RC:$dst, (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>; Given that it is an FMA pattern, the OpNode can be one of X86Fmadd, X86Fmsub (among other opnodes). The respective operations are : (a*b+c) and (a*b-c). My questions are: 1. Why does $src2 and not $src1 come first in (OpNode RC:$src2, RC:$src1, RC:$src3) ? In other words what is the difference between (a) and (b): (a) [(set RC:$dst, (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))] (b)...

I am trying to make some modifications to our code generator that will produce better code, but require adding new patterns. What I am trying to do is take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace =

I'm not at the machine that has the changes, but it was failing at index 0. Micah From: Owen Anderson [mailto:resistor at mac.com] Sent: Thursday, April 19, 2012 3:35 PM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output

..."\t{$src3, $src2, $dst|$dst, $src2, $src3}"), > [(set RC:$dst, > (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>; > > > Given that it is an FMA pattern, the OpNode can be one of X86Fmadd, > X86Fmsub (among other opnodes). The respective operations are : > (a*b+c) and (a*b-c). My questions are: > > 1. Why does $src2 and not $src1 come first in (OpNode RC:$src2, > RC:$src1, RC:$src3) ? In other words what is the difference between > (a) and (b): > (a) [(set RC:$dst, (OpVT (OpNode RC:$src2, R...

Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output from llc -debug, and matching it up with the state machine in your DAGISel.inc to see at what step the auto-generated matcher is failing to match your and-with-immediate? -Owen On Apr 19, 2012, at 3:07 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > I am trying to make

Right, it's failing when it tries to materialize a move of a constant into a register. But it's only trying to do that because it previously failed to fold the constant into the AND. What you need to do is step through the path it takes when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version.

I think that what I did originally should have worked and the bug was correct as I reported it. Here is an alternate implementation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList,

...rc2, $dst|$dst, $src2, > $src3}"), > > [(set RC:$dst, > > (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>; > > > > > > Given that it is an FMA pattern, the OpNode can be one of X86Fmadd, > > X86Fmsub (among other opnodes). The respective operations are : > > (a*b+c) and (a*b-c). My questions are: > > > > 1. Why does $src2 and not $src1 come first in (OpNode RC:$src2, > > RC:$src1, RC:$src3) ? In other words what is the difference between > > (a) and (b): > > (a) [(set RC:$...

This variant works: class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx,

In our generated asm code we've got a constraint such that two registers in a ternary op have to be in different "banks", best illustrated with an example: add r1,r2,r1 # r1 <- r2 + r1 The problem here is that the first operand (the receiver of the value) is in the same "bank" as the 3rd operand (r1 again). This will cause an extra cycle to be burned. As it turns

I have a simple test case that my code generator handles fine when using optimizations, but when I disable optimizations, It turns into a sequence of instructions that I can't figure out what to setup to get it to generate the correct code. The instructions in question are: %tmp1 = load float* %test ; <float> [#uses=1] %conv = fpext float %tmp1 to double ;

Hi, Justin > We're been writing multiclasses for each unique type of instruction. The > current PTX_LOGIC version is for 3-operand instructions. A new multiclass > needs to be created for 2-operand logic instructions. I am trying to add a multiclass for 2-operand logic instructions. For example, multiclass PTX_LOGIC_2OP<string opcstr, SDNode opnode> { def ripreds :

I'm confused about how to specify DAG patterns for a given instruction Here is an example for my target class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode> : ALU_RR<subOp, asmstr, [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>; def ADD : ALU1_RR<0x0, "l.add", add>; The set operation simply creates a list. The add operation

Not sure what you mean. I.OutOperandList == (outs CPU16Regs:$rx) I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) On 07/02/2012 09:26 PM, Sean Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args though... which makes me wonder what is

class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : // ... This class has template args. You don't specify them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote: > Not sure what you mean.

Hi, all I am trying to add "not" instruction support to PTX backend. I add the line below in PTXInstrInfo.td, defm NOT : PTX_LOGIC<"not", not>; But I get errors below, ------------------------------------------------------------------------------- Included from PTX.td:75: PTXInstrInfo.td:732:10: error: Value 'PTX_LOGIC::opnode' of type 'SDNode' is

In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; The SP can not be used in general purpose arithmetic instructions, therefore I defined the following

Hello. I have extended the BPF back end with vector registers (inspiring from Mips MSA) - something like this: def MSA128D: RegisterClass<"Connex", [v128i16], 32, (sequence "Wh%u", 0, 31)>; I also added vector store and load instructions in the style of Mips MSA - see

Is it legal to do something like a !strconcat on a non-string entity? That is, is there some operation that will let me do this (replace SOME_CONCAT with an appropriate operator): (WARNING! Hacked-up tablegen ahead!) multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, SDNode OpNode> { // Vector operation emulating scalar (fp)

<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> <html> <head> <meta content="text/html;charset=UTF-8" http-equiv="Content-Type"> </head> <body bgcolor="#ffffff" text="#000000"> 陳韋任 wrote: <blockquote cite="mid:20110509013918.GA13760@cs.nctu.edu.tw" type="cite">