search for: offsetimm

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2015 Jul 09
3
[LLVMdev] New backend help request.
Hmm, I'm getting nowhere pretty fast. It seems 68000 with its CISC nature is quite complex to implement for a novice. I can see how to implement simple stuff, like -- move dn, dn move dn, (an) As that just turns into stores, sets, etc. But how would you represent things like indexed access? move dn, (an,dn) move dn, offset(an) Can I only really define very simple operations for the main
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
But don't the defs for ADDR_RR and ADDR_RI also contain dags? def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; Do I need to create some other intermediate node type for a shifted address? Phil On Mon, Sep 26, 2016 at 1:42 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 9/26/2016 3:36 PM, Phil Tomson via llvm-dev wrote: > >> def ADDR_SHLI : Addr&l...
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
...ndInfo = opInfo; } let PrintMethod = "printMemOperand" in { def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; def ADDR_SHLI : Addr< 2, "SelectAddrShlImm", (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >; } If I change the LoadOpIdx definition to: class LoadOpIdx< bits<7> op, string instr_asm, OperandInfo in...
2016 Sep 28
2
Incompatible type assertion from llvm-tblgen
...nd ADDR_RI also contain dags? >> >> def ADDR_RR : Addr< 2, "SelectAddrRegReg", >> (ops GPRC:$base, GPRC:$offsetreg) >; >> def ADDR_RI : Addr< 2, "SelectAddrRegImm", >> (ops GPRC:$base, i64imm:$offsetimm) >; >> >> Do I need to create some other intermediate node type for a shifted >> address? >> > > Technically yes, but the list of allowed types is limited. "RegisterClass" > (e.g GPRC) is allowed, as is "Operand" (e.g. i64imm). > > You c...