search for: nvisa_gm107_chipset

Displaying 7 results from an estimated 7 matches for "nvisa_gm107_chipset".

Did you mean: nvisa_gk104_chipset
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
...= (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32; bld.mkCvt(OP_CVT, TYPE_U16, layer, sTy, src)->saturate = sat; - for (int s = dim; s >= 1; --s) - i->setSrc(s, i->getSrc(s - 1)); - i->setSrc(0, layer); + if (i->op != OP_TXD || chipset < NVISA_GM107_CHIPSET) { + for (int s = dim; s >= 1; --s) + i->setSrc(s, i->getSrc(s - 1)); + i->setSrc(0, layer); + } else { + i->setSrc(dim, layer); + } } // Move the indirect reference to the first place - if (i->tex.r...
2014 May 27
8
[PATCH 0/2] nvc0: support for GK20A (Tegra K1)
The following 2 patches make it possible to run Mesa programs on GK20A (Tegra K1). GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class as well as the same ISA as GK110 (SM35). Taking these differences into account is sufficient to successfully render simple off-screen buffers. Alexandre Courbot (2): nvc0: add GK20A 3D class nvc0: use SM35 ISA with GK20A
2014 May 27
1
[PATCH 2/2] nvc0: use SM35 ISA with GK20A
.../codegen/nv50_ir_driver.h > @@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol > #define NVISA_GF100_CHIPSET_C0 0xc0 > #define NVISA_GF100_CHIPSET_D0 0xd0 > #define NVISA_GK104_CHIPSET 0xe0 > +#define NVISA_GK20A_CHIPSET 0xea > #define NVISA_GK110_CHIPSET 0xf0 > #define NVISA_GM107_CHIPSET 0x110 > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > index b1f76cf80432..f69e6a183e19 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > +++ b/src/gallium/drivers/nouv...
2014 May 27
0
[PATCH 2/2] nvc0: use SM35 ISA with GK20A
...h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h @@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol #define NVISA_GF100_CHIPSET_C0 0xc0 #define NVISA_GF100_CHIPSET_D0 0xd0 #define NVISA_GK104_CHIPSET 0xe0 +#define NVISA_GK20A_CHIPSET 0xea #define NVISA_GK110_CHIPSET 0xf0 #define NVISA_GM107_CHIPSET 0x110 diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index b1f76cf80432..f69e6a183e19 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emi...
2014 May 27
0
[PATCH v2 2/2] nvc0: use SM35 ISA with GK20A
...h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h @@ -91,7 +91,7 @@ struct nv50_ir_prog_symbol #define NVISA_GF100_CHIPSET_C0 0xc0 #define NVISA_GF100_CHIPSET_D0 0xd0 #define NVISA_GK104_CHIPSET 0xe0 -#define NVISA_GK110_CHIPSET 0xf0 +#define NVISA_GK20A_CHIPSET 0xea #define NVISA_GM107_CHIPSET 0x110 struct nv50_ir_prog_info diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index b1f76cf80432..f69e6a183e19 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/n...
2017 Mar 26
5
[PATCH v5 0/5] nvc0/ir: add support for MAD/FMA PostRALoadPropagation
was "nv50/ir: PostRaConstantFolding improvements" before. nothing really changed from the last version, just minor things. Karol Herbst (5): nv50/ir: restructure and rename postraconstantfolding pass nv50/ir: implement mad post ra folding for nvc0+ gk110/ir: add LIMM form of mad gm107/ir: add LIMM form of mad nv50/ir: also do PostRaLoadPropagation for FMA
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
...n/nv50_ir_lowering_nvc0.cpp @@ -1802,6 +1802,9 @@ NVC0LoweringPass::loadSuInfo32(Value *ptr, int slot, uint32_t off, bool bindless { uint32_t base = slot * NVC0_SU_INFO__STRIDE; + // We don't upload surface info for bindless for GM107+ + assert(!bindless || targ->getChipset() < NVISA_GM107_CHIPSET); + if (ptr) { ptr = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getSSA(), ptr, bld.mkImm(slot)); if (bindless) @@ -2204,7 +2207,7 @@ getDestType(const ImgType type) { } void -NVC0LoweringPass::convertSurfaceFormat(TexInstruction *su) +NVC0LoweringPass::convertSurfaceFormat(TexInstructio...