Displaying 12 results from an estimated 12 matches for "nvisa_gk104_chipset".
2014 Mar 20
0
[PATCH] nvc0/ir: move sample id to second source arg to fix sampler2DMS
...onst int dim = i->tex.target.getDim() + i->tex.target.isCube();
const int arg = i->tex.target.getArgCount();
const int lyr = arg - (i->tex.target.isMS() ? 2 : 1);
+ const int chipset = prog->getTarget()->getChipset();
- if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) {
+ if (chipset >= NVISA_GK104_CHIPSET) {
if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
WARN("indirect TEX not implemented\n");
}
@@ -697,7 +698,7 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
}
} else
// (nvc0) ge...
2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index f010767..4a9e48f 100644
---
2014 May 27
8
[PATCH 0/2] nvc0: support for GK20A (Tegra K1)
The following 2 patches make it possible to run Mesa programs on GK20A
(Tegra K1).
GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class
as well as the same ISA as GK110 (SM35). Taking these differences into account
is sufficient to successfully render simple off-screen buffers.
Alexandre Courbot (2):
nvc0: add GK20A 3D class
nvc0: use SM35 ISA with GK20A
2014 May 27
1
[PATCH 2/2] nvc0: use SM35 ISA with GK20A
...2e..aab857ee7e4f 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> @@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol
> #define NVISA_GF100_CHIPSET_C0 0xc0
> #define NVISA_GF100_CHIPSET_D0 0xd0
> #define NVISA_GK104_CHIPSET 0xe0
> +#define NVISA_GK20A_CHIPSET 0xea
> #define NVISA_GK110_CHIPSET 0xf0
> #define NVISA_GM107_CHIPSET 0x110
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
> index b1f76cf80432...
2016 Mar 16
2
[PATCH mesa 5/6] nouveau: codegen: Add support for OpenCL global memory buffers
...e FILE_MEMORY_GLOBAL:
> + opc = 0x90000000;
> + break;
> + case FILE_MEMORY_LOCAL:
> + opc = 0xc8000000;
> + break;
> case FILE_MEMORY_SHARED:
> if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
> if (targ->getChipset() >= NVISA_GK104_CHIPSET)
> @@ -1828,8 +1835,13 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
> code[0] = 0x00000005;
>
> switch (i->src(0).getFile()) {
> - case FILE_MEMORY_BUFFER: opc = 0x80000000; break;
> - case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
> + case FILE_MEMO...
2016 Mar 16
0
[PATCH mesa 5/6] nouveau: codegen: Add support for OpenCL global memory buffers
...break;
+ case FILE_MEMORY_BUFFER:
+ case FILE_MEMORY_GLOBAL:
+ opc = 0x90000000;
+ break;
+ case FILE_MEMORY_LOCAL:
+ opc = 0xc8000000;
+ break;
case FILE_MEMORY_SHARED:
if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
if (targ->getChipset() >= NVISA_GK104_CHIPSET)
@@ -1828,8 +1835,13 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
code[0] = 0x00000005;
switch (i->src(0).getFile()) {
- case FILE_MEMORY_BUFFER: opc = 0x80000000; break;
- case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;
+ case FILE_MEMORY_BUFFER:
+ case FILE_MEMORY_GLO...
2014 May 27
0
[PATCH 2/2] nvc0: use SM35 ISA with GK20A
...0_ir_driver.h
index bbb89d97932e..aab857ee7e4f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol
#define NVISA_GF100_CHIPSET_C0 0xc0
#define NVISA_GF100_CHIPSET_D0 0xd0
#define NVISA_GK104_CHIPSET 0xe0
+#define NVISA_GK20A_CHIPSET 0xea
#define NVISA_GK110_CHIPSET 0xf0
#define NVISA_GM107_CHIPSET 0x110
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index b1f76cf80432..f69e6a183e19 100644
--- a/...
2014 May 27
0
[PATCH v2 2/2] nvc0: use SM35 ISA with GK20A
...0_ir_driver.h
index bbb89d97932e..f829aac0bcc2 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -91,7 +91,7 @@ struct nv50_ir_prog_symbol
#define NVISA_GF100_CHIPSET_C0 0xc0
#define NVISA_GF100_CHIPSET_D0 0xd0
#define NVISA_GK104_CHIPSET 0xe0
-#define NVISA_GK110_CHIPSET 0xf0
+#define NVISA_GK20A_CHIPSET 0xea
#define NVISA_GM107_CHIPSET 0x110
struct nv50_ir_prog_info
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index b1f76cf80432.....
2015 Jan 04
0
[PATCH] nv50/ir: fix texture offsets in release builds
...set[0][c].getImmediate(val));
+ if (!i->offset[0][c].getImmediate(val))
+ assert(!"non-immediate offset passed to non-TXG");
imm |= (val.reg.data.u32 & 0xf) << (c * 4);
}
if (i->op == OP_TXD && chipset >= NVISA_GK104_CHIPSET) {
--
2.0.5
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
...with array)
+ //
+ // Maxwell (tex):
+ // array
+ // coords
+ // indirect handle
+ // sample
+ // lod bias
+ // depth compare
+ // offsets
+ //
+ // Maxwell (txd):
+ // indirect handle
+ // coords
+ // array + offsets
+ // derivatives
if (chipset >= NVISA_GK104_CHIPSET) {
if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) {
@@ -634,12 +649,17 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
const int sat = (i->op == OP_TXF) ? 1 : 0;
DataType sTy = (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32;
bld.mkCvt(OP_...
2016 Mar 16
0
[PATCH mesa 5/6] nouveau: codegen: Add support for OpenCL global memory buffers
...opc = 0x90000000;
>> + break;
>> + case FILE_MEMORY_LOCAL:
>> + opc = 0xc8000000;
>> + break;
>> case FILE_MEMORY_SHARED:
>> if (i->subOp == NV50_IR_SUBOP_STORE_UNLOCKED) {
>> if (targ->getChipset() >= NVISA_GK104_CHIPSET)
>> @@ -1828,8 +1835,13 @@ CodeEmitterNVC0::emitLOAD(const Instruction *i)
>> code[0] = 0x00000005;
>>
>> switch (i->src(0).getFile()) {
>> - case FILE_MEMORY_BUFFER: opc = 0x80000000; break;
>> - case FILE_MEMORY_LOCAL: opc = 0xc0000000; break;...
2016 Mar 16
13
[PATCH mesa 1/6] tgsi_build: Fix return of uninitialized memory in tgsi_*_instruction_memory
tgsi_default_instruction_memory / tgsi_build_instruction_memory were
returning uninitialized memory for tgsi_instruction_memory.Texture and
tgsi_instruction_memory.Format. Note 0 means not set, and thus is a
correct default initializer for these.
Fixes: 3243b6fc97 ("tgsi: add Texture and Format to tgsi_instruction_memory")
Cc: Nicolai Hähnle <nicolai.haehnle at amd.com>