search for: nreg

Displaying 20 results from an estimated 20 matches for "nreg".

Did you mean: greg
2011 Jan 28
2
[LLVMdev] The type or size of virtual registers
...ks for your help with me about the way to access type and size of Value. But, I want also know the interface for me to access the type or size of virtual registers in the SSA form. 1. I find no way to associate the virtual registers with the Value class. 2. I also tried to get the size of register nReg by: TargetRegisterClass::getSize(), where the TargetRegisterClass object is obtained by MachineRegisterInfo::getRegClass( nReg ). But, I found it always returned with the value 4 bytes, say, GR32 (My target is the x86-32 bits). If all virtual registers were size of 32 bits, how could we conside...
2010 Feb 12
2
Function Fstats and p value
Hello, I used the function Fstats (in the package strucchange) and would like to transform the F probability given by Fstats in P value. This transformation can be made while making a plot, but I need to have the numerical P value which are ploted... and I can't find out how to do. Here a is an exemple, to plot the P value. let's take data as a array fs <-fstats(data ~ 1, from = 4,
2006 Apr 18
1
Nonlinear Regression model: Diagnostics
Hi, I am trying to run the following nonlinear regression model. > nreg <- nls(y ~ exp(-b*x), data = mydf, start = list(b = 0), alg = "default", trace = TRUE) OUTPUT: 24619327 : 0 24593178 : 0.0001166910 24555219 : 0.0005019005 24521810 : 0.001341571 24500774 : 0.002705402 24490713 : 0.004401078 24486658 : 0.00607728 24485115 : 0.00...
2011 Jan 28
0
[LLVMdev] The type or size of virtual registers
...In the in-memory LLVM IR, all of the SSA values are C++ objects derived from the Value class. For example, an Instruction object (class Instruction derives from class Value) *is* the SSA value generated by its result; they are one and the same. > 2. I also tried to get the size of register nReg by: > TargetRegisterClass::getSize(), where the TargetRegisterClass object > is obtained by MachineRegisterInfo::getRegClass( nReg ). > But, I found it always returned with the value 4 bytes, say, GR32 (My > target is the x86-32 bits). If all virtual registers were size of 32 &gt...
2011 Jan 29
1
[LLVMdev] The type or size of virtual registers
...IR, all of the SSA values are C++ objects derived > from the Value class. For example, an Instruction object (class Instruction > derives from class Value) *is* the SSA value generated by its result; they > are one and the same. > > > 2. I also tried to get the size of register nReg by: > TargetRegisterClass::getSize(), where the TargetRegisterClass object is > obtained by MachineRegisterInfo::getRegClass( nReg ). > But, I found it always returned with the value 4 bytes, say, GR32 (My > target is the x86-32 bits). If all virtual registers were size of 32 bits,...
2011 Jan 27
0
[LLVMdev] The type or size of virtual registers
On 1/27/11 3:23 AM, Qingan Li wrote: > Hi, > > I wonder if there is an interface for me to access the type or size of > virtual registers in the SSA form? > I have scanned the MachineOperand in CodeGen part, and failed to find > this kind of info for virtual registers. The getType() method of Value * will return the LLVM type. The TargetData class will provide information on
2011 Jan 27
2
[LLVMdev] The type or size of virtual registers
Hi, I wonder if there is an interface for me to access the type or size of virtual registers in the SSA form? I have scanned the MachineOperand in CodeGen part, and failed to find this kind of info for virtual registers. -- Best regards, Li Qingan -------------- next part -------------- An HTML attachment was scrubbed... URL:
2008 Feb 26
8
[PATCH 0/8] RFC: ia64/xen TAKE 2: paravirtualization of hand written assembly code
Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place
2008 Feb 26
8
[PATCH 0/8] RFC: ia64/xen TAKE 2: paravirtualization of hand written assembly code
Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place
2019 Mar 14
2
inline assembly matching error
I'm trying to add support for inline assembly and I keep getting this error: <jal> "<inline asm>:1:2: error: invalid instruction" which is due to the fact that MatchInstructionImpl() returns Match_MnemonicFail. This function is tablegen'ed in XXXGenAsmMatcher.inc and for some reason it can't find JAL even though I can clearly see it in both MatchTable0[] and
2004 Apr 24
4
Moving window regressions - how can I improve this code?
I wrote a function which does "moving window" regressions. E.g. if there are 100 observations and the window width is 50, then I first run the regression for observations 1..50, then for 2..51, and so on. I am extremely pleased with R in my experience with writing this, since I was able to pass the model as an argument into the function :-) Forgive me if I sound naive, but that's
2009 Jan 18
1
auto.arima forecasting issue
...been able to solve. I use this function on time series that contains NA values, but every time that the resulting model contains drift I can't perform a forecasting (using forecast.Arima function). The printed error (when I try to forecast the resulting model) claims a dimension mismatch "nreg=newxreg" Here is what I've been triyng to do >ser<-auto.arima(x,start.p=0,start.q=0,start.P=0,start.Q=0,trace=TRUE,stepwise=TRUE); >forecast(ser,h=12) x is ts object (-monthly data-) Thanks [[alternative HTML version deleted]]
2008 Feb 25
6
[PATCH 0/4] ia64/xen: paravirtualization of hand written assembly code
Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested
2008 Feb 25
6
[PATCH 0/4] ia64/xen: paravirtualization of hand written assembly code
Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested
2008 Mar 05
51
[PATCH 00/50] ia64/xen take 3: ia64/xen domU paravirtualization
Hi. This patchset implements xen/ia64 domU support. Qing He and Eddie Dong also has been woring on pv_ops so that I want to discuss before going further and avoid duplicated work. I suppose that Eddie will also post his own patch. So reviewing both patches, we can reach to better pv_ops interface. - I didn't changed the ia64 intrinsic paravirtulization abi from the last post. Presumably it
2008 Mar 05
51
[PATCH 00/50] ia64/xen take 3: ia64/xen domU paravirtualization
Hi. This patchset implements xen/ia64 domU support. Qing He and Eddie Dong also has been woring on pv_ops so that I want to discuss before going further and avoid duplicated work. I suppose that Eddie will also post his own patch. So reviewing both patches, we can reach to better pv_ops interface. - I didn't changed the ia64 intrinsic paravirtulization abi from the last post. Presumably it
2012 Mar 23
12
[PATCH RFC V5 0/6] kvm : Paravirt-spinlock support for KVM guests
The 6-patch series to follow this email extends KVM-hypervisor and Linux guest running on KVM-hypervisor to support pv-ticket spinlocks, based on Xen's implementation. One hypercall is introduced in KVM hypervisor,that allows a vcpu to kick another vcpu out of halt state. The blocking of vcpu is done using halt() in (lock_spinning) slowpath. one MSR is added to aid live migration. Changes
2012 Mar 23
12
[PATCH RFC V5 0/6] kvm : Paravirt-spinlock support for KVM guests
The 6-patch series to follow this email extends KVM-hypervisor and Linux guest running on KVM-hypervisor to support pv-ticket spinlocks, based on Xen's implementation. One hypercall is introduced in KVM hypervisor,that allows a vcpu to kick another vcpu out of halt state. The blocking of vcpu is done using halt() in (lock_spinning) slowpath. one MSR is added to aid live migration. Changes
2020 Mar 05
55
[PATCH 00/22] drm: Convert drivers to drm_simple_encoder_init()
A call to drm_simple_encoder_init() initializes an encoder without further functionality. It only provides the destroy callback to cleanup the encoder's state. Only few drivers implement more sophisticated encoders than that. Most drivers implement such a simple encoder and can use drm_simple_encoder_init() instead. The patchset converts drivers where the encoder's instance is embedded in
2020 Mar 05
55
[PATCH 00/22] drm: Convert drivers to drm_simple_encoder_init()
A call to drm_simple_encoder_init() initializes an encoder without further functionality. It only provides the destroy callback to cleanup the encoder's state. Only few drivers implement more sophisticated encoders than that. Most drivers implement such a simple encoder and can use drm_simple_encoder_init() instead. The patchset converts drivers where the encoder's instance is embedded in