search for: nouveau_pll_vals

...rs/gpu/drm/nouveau/core/include/subdev/clock.h index 39e73b9..41b7a6a 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h @@ -54,6 +54,7 @@ int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, int clk, struct nouveau_pll_vals *); int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, struct nouveau_pll_vals *); - +int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, + int clk, struct nouveau_pll_vals *); #endif diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/n...

.../clock.h >> index 36ed035d4d42..6c36f0e4385b 100644 >> --- a/nvkm/include/subdev/clock.h >> +++ b/nvkm/include/subdev/clock.h >> @@ -159,7 +159,7 @@ int nva3_clock_pll_calc(struct nouveau_clock *, struct >> nvbios_pll *, >> int clk, struct nouveau_pll_vals *); >> int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr); >> -int nouveau_clock_astate(struct nouveau_clock *, int req, int rel); >> +int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool >> wait); >> int nouveau_clock_dstate(st...

Resend of patch #7 to fix behaviour when failing to pause parts of the GPU

...letions(-) diff --git a/nvkm/include/subdev/clock.h b/nvkm/include/subdev/clock.h index 36ed035d4d42..6c36f0e4385b 100644 --- a/nvkm/include/subdev/clock.h +++ b/nvkm/include/subdev/clock.h @@ -159,7 +159,7 @@ int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, int clk, struct nouveau_pll_vals *); int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr); -int nouveau_clock_astate(struct nouveau_clock *, int req, int rel); +int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool wait); int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel); int n...

...vkm/include/subdev/clock.h b/nvkm/include/subdev/clock.h > index 36ed035d4d42..6c36f0e4385b 100644 > --- a/nvkm/include/subdev/clock.h > +++ b/nvkm/include/subdev/clock.h > @@ -159,7 +159,7 @@ int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, > int clk, struct nouveau_pll_vals *); > > int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr); > -int nouveau_clock_astate(struct nouveau_clock *, int req, int rel); > +int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool wait); > int nouveau_clock_dstate(struct nouveau_clock...

....52e65b8 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h @@ -146,6 +146,9 @@ int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, int clk, struct nouveau_pll_vals *); +int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags); +void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags); + int nouveau_clock_ustate(struct nouveau_clock *, int req); int nouveau_clock_astate(struct nouveau_clock *, int req, int rel); int nouveau_clock_d...

....52e65b8 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h @@ -146,6 +146,9 @@ int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, int clk, struct nouveau_pll_vals *); +int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags); +void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags); + int nouveau_clock_ustate(struct nouveau_clock *, int req); int nouveau_clock_astate(struct nouveau_clock *, int req, int rel); int nouveau_clock_d...

...987a9..ea55a41 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -358,7 +358,6 @@ struct nouveau_engine { struct nouveau_fb_engine fb; struct nouveau_pgraph_engine graph; struct nouveau_fifo_engine fifo; - spinlock_t lock; }; struct nouveau_pll_vals { @@ -534,6 +533,9 @@ struct drm_nouveau_private { struct nouveau_engine engine; struct nouveau_channel *channel; + /* For PFIFO and PGRAPH. */ + spinlock_t context_switch_lock; + /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ struct nouveau_gpuobj *ramht; uint32_t ramin_rsvd...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- I decided to let the user still specify config=BLA=1 to override the hw disable in case we get something wrong or for double-checking stuff, but I suspect it won't really be used much. I'm not terribly fond of the message text, if you come up with something better, feel free to drop it in.

Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved. These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated

..._state_ext(struct drm_crtc *crtc, struct drm_display_mod struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nv04_mode_state *state = &dev_priv->mode_reg; struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; - struct drm_framebuffer *fb = crtc->fb; struct nouveau_pll_vals *pv = &regp->pllvals; struct pll_lims pll_lim; - int vclk, arb_burst, arb_fifo_lwm; if (get_pll_limits(dev, nv_crtc->index ? VPLL2 : VPLL1, &pll_lim)) return; @@ -130,8 +128,7 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod if (dev_priv-&...

Hi, This is a try to have some simple DVFS (Dynamic Voltage and Frequency Scaling) support for GK20A. Instead of relying on other existing frequency scaling framework, we create a simple subdev in Nouveau for the same purpose. That's because we don't want to make the DVFS implementation for GK20A far more than enough in the beginning and hinder the implementation for dGPU in the future.

It seems it was only locking up in the context of nouveau_hw_save_vga_fonts, when it actually did something (because the console wasn't already in graphics mode). Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- drivers/gpu/drm/nouveau/nouveau_hw.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c

This patch series adds TV-out modesetting support to the KMS implementation. I've tried to test it on all the hardware I've got at hand (that is nv11, nv17, nv34, nv35, nv40, nv4b) with every possible output combination; I believe it has reached a mergeable state, however it depends on some commits from drm-next that haven't got into Linus' tree yet, if you agree to merge this