Nouveau - Jan 2015 - [PATCH V2 1/4] clk: allow non-blocking for nouveau_clock_astate()

There might be some callers of nouveau_clock_astate(), and they are from
inetrrupt context. So we must ensure that this function can be atomic in
that condition. This patch adds one parameter which is subsequently passed
to nouveau_pstate_calc(). Therefore we can choose whether we want to wait
for the pstate work's completion or not.

Signed-off-by: Vince Hsu <vinceh at nvidia.com>
---

v2: none. (v1 is the RFC actually)

 nvkm/include/subdev/clock.h | 2 +-
 nvkm/subdev/clock/base.c    | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/nvkm/include/subdev/clock.h b/nvkm/include/subdev/clock.h
index 36ed035d4d42..6c36f0e4385b 100644
--- a/nvkm/include/subdev/clock.h
+++ b/nvkm/include/subdev/clock.h
@@ -159,7 +159,7 @@ int nva3_clock_pll_calc(struct nouveau_clock *, struct
nvbios_pll *,
 			int clk, struct nouveau_pll_vals *);
 
 int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr);
-int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
+int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool wait);
 int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
 int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
 
diff --git a/nvkm/subdev/clock/base.c b/nvkm/subdev/clock/base.c
index e51b72d47129..b1bbe764fa35 100644
--- a/nvkm/subdev/clock/base.c
+++ b/nvkm/subdev/clock/base.c
@@ -430,13 +430,13 @@ nouveau_clock_ustate(struct nouveau_clock *clk, int req,
int pwr)
 }
 
 int
-nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
+nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool wait)
 {
 	if (!rel) clk->astate  = req;
 	if ( rel) clk->astate += rel;
 	clk->astate = min(clk->astate, clk->state_nr - 1);
 	clk->astate = max(clk->astate, 0);
-	return nouveau_pstate_calc(clk, true);
+	return nouveau_pstate_calc(clk, wait);
 }
 
 int
-- 
1.9.1

The platform device does not use the common nouveau_pwr_init() to initialize
the PWR, but it does need the .prob() be assigned to avoid NULL pointer
dereference in graph/nve4.c.

Signed-off-by: Vince Hsu <vinceh at nvidia.com>
---

v2: this patch is added since v2. (v1 is the RFC actually)

 nvkm/subdev/pwr/base.c | 2 +-
 nvkm/subdev/pwr/priv.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/nvkm/subdev/pwr/base.c b/nvkm/subdev/pwr/base.c
index 0ab55f27ec45..1ea433a5e118 100644
--- a/nvkm/subdev/pwr/base.c
+++ b/nvkm/subdev/pwr/base.c
@@ -26,7 +26,7 @@
 
 #include "priv.h"
 
-static void
+void
 nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
 {
 	const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr);
diff --git a/nvkm/subdev/pwr/priv.h b/nvkm/subdev/pwr/priv.h
index 3814a341db32..86149d9a440c 100644
--- a/nvkm/subdev/pwr/priv.h
+++ b/nvkm/subdev/pwr/priv.h
@@ -26,6 +26,7 @@ int _nouveau_pwr_ctor(struct nouveau_object *, struct
nouveau_object *,
 #define _nouveau_pwr_dtor _nouveau_subdev_dtor
 int _nouveau_pwr_init(struct nouveau_object *);
 int _nouveau_pwr_fini(struct nouveau_object *, bool);
+void nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable);
 
 struct nvkm_pwr_impl {
 	struct nouveau_oclass base;
-- 
1.9.1

This patch adds PWR support for GK20A. But instead of adding the PWR features
like firmware loading and communication with PMU firmware, we add the DVFS
(Dynamic Voltage and Frequency Scaling), which is one of the PMU firmware's
jobs on dGPUs, in this patch. This refers to the idle signals provided by the
NVIDIA hardware and tries to adjust the performance level based on the
calculated target. The reclocking policy can be fine-tuned later when we have
more real use cases.

Signed-off-by: Vince Hsu <vinceh at nvidia.com>
---

v2: moved the dvfs to pwr subdev. (v1 is the RFC)


 drm/Kbuild                  |   1 +
 drm/core/subdev/pwr/gk20a.c |   1 +
 nvkm/engine/device/nve0.c   |   1 +
 nvkm/include/subdev/pwr.h   |   1 +
 nvkm/subdev/pwr/Makefile.am |   3 +-
 nvkm/subdev/pwr/gk20a.c     | 232 ++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 238 insertions(+), 1 deletion(-)
 create mode 120000 drm/core/subdev/pwr/gk20a.c
 create mode 100644 nvkm/subdev/pwr/gk20a.c

diff --git a/drm/Kbuild b/drm/Kbuild
index 06556136deb5..d513c7e52f2c 100644
--- a/drm/Kbuild
+++ b/drm/Kbuild
@@ -202,6 +202,7 @@ nouveau-y += core/subdev/pwr/nvc0.o
 nouveau-y += core/subdev/pwr/nvd0.o
 nouveau-y += core/subdev/pwr/gk104.o
 nouveau-y += core/subdev/pwr/nv108.o
+nouveau-y += core/subdev/pwr/gk20a.o
 nouveau-y += core/subdev/therm/base.o
 nouveau-y += core/subdev/therm/fan.o
 nouveau-y += core/subdev/therm/fannil.o
diff --git a/drm/core/subdev/pwr/gk20a.c b/drm/core/subdev/pwr/gk20a.c
new file mode 120000
index 000000000000..804979982c34
--- /dev/null
+++ b/drm/core/subdev/pwr/gk20a.c
@@ -0,0 +1 @@
+../../../../nvkm/subdev/pwr/gk20a.c
\ No newline at end of file
diff --git a/nvkm/engine/device/nve0.c b/nvkm/engine/device/nve0.c
index 98e7d6485f43..1f7acd31c498 100644
--- a/nvkm/engine/device/nve0.c
+++ b/nvkm/engine/device/nve0.c
@@ -180,6 +180,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
 		device->oclass[NVDEV_ENGINE_PERFMON] = &gk20a_perfmon_oclass;
 		device->oclass[NVDEV_SUBDEV_VOLT   ] = &gk20a_volt_oclass;
+		device->oclass[NVDEV_SUBDEV_PWR    ] =  gk20a_pwr_oclass;
 		break;
 	case 0xf0:
 		device->cname = "GK110";
diff --git a/nvkm/include/subdev/pwr.h b/nvkm/include/subdev/pwr.h
index f2427bf5aeed..535a410674e5 100644
--- a/nvkm/include/subdev/pwr.h
+++ b/nvkm/include/subdev/pwr.h
@@ -38,6 +38,7 @@ extern struct nouveau_oclass *nvc0_pwr_oclass;
 extern struct nouveau_oclass *nvd0_pwr_oclass;
 extern struct nouveau_oclass *gk104_pwr_oclass;
 extern struct nouveau_oclass *nv108_pwr_oclass;
+extern struct nouveau_oclass *gk20a_pwr_oclass;
 
 /* interface to MEMX process running on PPWR */
 struct nouveau_memx;
diff --git a/nvkm/subdev/pwr/Makefile.am b/nvkm/subdev/pwr/Makefile.am
index 2bb4ca666c58..f59eec0522cc 100644
--- a/nvkm/subdev/pwr/Makefile.am
+++ b/nvkm/subdev/pwr/Makefile.am
@@ -12,7 +12,8 @@ libpwr_la_SOURCES = base.c \
 		    nvc0.c \
 		    nvd0.c \
 		    gk104.c \
-		    nv108.c
+		    nv108.c \
+		    gk20a.c
 
 FUC_COMMON = fuc/os.h \
 	     fuc/macros.fuc \
diff --git a/nvkm/subdev/pwr/gk20a.c b/nvkm/subdev/pwr/gk20a.c
new file mode 100644
index 000000000000..f6b7df1b1686
--- /dev/null
+++ b/nvkm/subdev/pwr/gk20a.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
"Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#include "priv.h"
+
+#include <subdev/clock.h>
+#include <subdev/timer.h>
+#include <subdev/volt.h>
+
+#define BUSY_SLOT	0
+#define CLK_SLOT	7
+
+struct gk20a_pwr_dvfs_data {
+	int p_load_target;
+	int p_load_max;
+	int p_smooth;
+	unsigned int avg_load;
+};
+
+struct gk20a_pwr_priv {
+	struct nouveau_pwr base;
+	struct nouveau_alarm alarm;
+	struct gk20a_pwr_dvfs_data *data;
+};
+
+struct gk20a_pwr_dvfs_dev_status {
+	unsigned long total;
+	unsigned long busy;
+	int cur_state;
+};
+
+static int
+gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state)
+{
+	struct nouveau_clock *clk = nouveau_clock(priv);
+
+	return nouveau_clock_astate(clk, *state, 0, false);
+}
+
+static int
+gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state)
+{
+	struct nouveau_clock *clk = nouveau_clock(priv);
+
+	*state = clk->pstate;
+	return 0;
+}
+
+static int
+gk20a_pwr_dvfs_get_target_state(struct gk20a_pwr_priv *priv,
+		int *state, int load)
+{
+	struct gk20a_pwr_dvfs_data *data = priv->data;
+	struct nouveau_clock *clk = nouveau_clock(priv);
+	int cur_level, level;
+
+	/* For GK20A, the performance level is directly mapped to pstate */
+	level = cur_level = clk->pstate;
+
+	if (load > data->p_load_max) {
+		level = min(clk->state_nr - 1, level + (clk->state_nr / 3));
+	} else {
+		level += ((load - data->p_load_target) * 10 /
+				data->p_load_target) / 2;
+		level = max(0, level);
+		level = min(clk->state_nr - 1, level);
+	}
+
+	nv_trace(priv, "cur level = %d, new level = %d\n", cur_level,
level);
+
+	*state = level;
+
+	if (level == cur_level)
+		return 0;
+	else
+		return 1;
+}
+
+static int
+gk20a_pwr_dvfs_get_dev_status(struct gk20a_pwr_priv *priv,
+		struct gk20a_pwr_dvfs_dev_status *status)
+{
+	status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10));
+	status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10));
+	return 0;
+}
+
+static void
+gk20a_pwr_dvfs_reset_dev_status(struct gk20a_pwr_priv *priv)
+{
+	nv_wr32(priv, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000);
+	nv_wr32(priv, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000);
+}
+
+static void
+gk20a_pwr_dvfs_work(struct nouveau_alarm *alarm)
+{
+	struct gk20a_pwr_priv *priv = container_of(alarm,
+					struct gk20a_pwr_priv, alarm);
+	struct gk20a_pwr_dvfs_data *data = priv->data;
+	struct gk20a_pwr_dvfs_dev_status status;
+	struct nouveau_clock *clk = nouveau_clock(priv);
+	struct nouveau_volt *volt = nouveau_volt(priv);
+	u32 utilization = 0;
+	int state, ret;
+
+	/*
+	 * The PWR is initialized before CLK and VOLT, so we have to make sure the
+	 * CLK and VOLT are ready here.
+	 */
+	if (!clk || !volt)
+		goto resched;
+
+	ret = gk20a_pwr_dvfs_get_dev_status(priv, &status);
+	if (ret) {
+		nv_warn(priv, "failed to get device status\n");
+		goto resched;
+	}
+
+	if (status.total)
+		utilization = div_u64((u64)status.busy * 100, status.total);
+
+	data->avg_load = (data->p_smooth * data->avg_load) + utilization;
+	data->avg_load /= data->p_smooth + 1;
+	nv_trace(priv, "utilization = %d %%, avg_load = %d %%\n",
+			utilization, data->avg_load);
+
+	ret = gk20a_pwr_dvfs_get_cur_state(priv, &state);
+	if (ret) {
+		nv_warn(priv, "failed to get current state\n");
+		goto resched;
+	}
+
+	if (gk20a_pwr_dvfs_get_target_state(priv, &state, data->avg_load)) {
+		nv_trace(priv, "set new state to %d\n", state);
+		gk20a_pwr_dvfs_target(priv, &state);
+	}
+
+resched:
+	gk20a_pwr_dvfs_reset_dev_status(priv);
+	nouveau_timer_alarm(priv, 100000000, alarm);
+}
+
+int
+gk20a_pwr_fini(struct nouveau_object *object, bool suspend)
+{
+	struct nouveau_pwr *ppwr = (void *)object;
+	struct gk20a_pwr_priv *priv = (void *)ppwr;
+
+	nouveau_timer_alarm_cancel(priv, &priv->alarm);
+
+	return nouveau_subdev_fini(&ppwr->base, suspend);
+}
+
+int
+gk20a_pwr_init(struct nouveau_object *object)
+{
+	struct nouveau_pwr *ppwr = (void *)object;
+	struct gk20a_pwr_priv *priv = (void *)ppwr;
+	int ret;
+
+	ret = nouveau_subdev_init(&ppwr->base);
+	if (ret)
+		return ret;
+
+	ppwr->pgob = nouveau_pwr_pgob;
+
+	/* init pwr perf counter */
+	nv_wr32(ppwr, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
+	nv_wr32(ppwr, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
+	nv_wr32(ppwr, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
+
+	nouveau_timer_alarm(ppwr, 2000000000, &priv->alarm);
+
+	return ret;
+}
+
+struct gk20a_pwr_dvfs_data gk20a_dvfs_data= {
+	.p_load_target = 70,
+	.p_load_max = 90,
+	.p_smooth = 1,
+};
+
+static int
+gk20a_pwr_ctor(struct nouveau_object *parent,
+		  struct nouveau_object *engine,
+		  struct nouveau_oclass *oclass, void *data, u32 size,
+		  struct nouveau_object **pobject)
+{
+	struct gk20a_pwr_priv *priv;
+	int ret;
+
+	ret = nouveau_pwr_create(parent, engine, oclass, &priv);
+	*pobject = nv_object(priv);
+	if (ret)
+		return ret;
+
+	priv->data = &gk20a_dvfs_data;
+
+	nouveau_alarm_init(&priv->alarm, gk20a_pwr_dvfs_work);
+
+	return 0;
+}
+
+struct nouveau_oclass *
+gk20a_pwr_oclass = &(struct nvkm_pwr_impl) {
+	.base.handle = NV_SUBDEV(PWR, 0xea),
+	.base.ofuncs = &(struct nouveau_ofuncs) {
+		.ctor = gk20a_pwr_ctor,
+		.dtor = _nouveau_pwr_dtor,
+		.init = gk20a_pwr_init,
+		.fini = gk20a_pwr_fini,
+	},
+}.base;
-- 
1.9.1

This patch adds one option for the boot config strings "NvClkMode*",
so
that we can enable the "auto" mode when loading module.

Signed-off-by: Vince Hsu <vinceh at nvidia.com>
---

v2: none. (v1 is the RFC)

 nvkm/subdev/clock/base.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/nvkm/subdev/clock/base.c b/nvkm/subdev/clock/base.c
index b1bbe764fa35..bc095b470121 100644
--- a/nvkm/subdev/clock/base.c
+++ b/nvkm/subdev/clock/base.c
@@ -401,6 +401,9 @@ nouveau_clock_nstate(struct nouveau_clock *clk, const char
*mode, int arglen)
 {
 	int ret = 1;
 
+	if (clk->allow_reclock && !strncasecmpz(mode, "auto",
arglen))
+		return -2;
+
 	if (strncasecmpz(mode, "disabled", arglen)) {
 		char save = mode[arglen];
 		long v;
-- 
1.9.1

On 12/22/2014 05:11 PM, Vince Hsu wrote:
> The platform device does not use the common nouveau_pwr_init() to
initialize
> the PWR, but it does need the .prob() be assigned to avoid NULL pointer
> dereference in graph/nve4.c.
s/prob/pgob/  :-(
Will fix in next version.
>
> Signed-off-by: Vince Hsu <vinceh at nvidia.com>
> ---
>
> v2: this patch is added since v2. (v1 is the RFC actually)
>
>   nvkm/subdev/pwr/base.c | 2 +-
>   nvkm/subdev/pwr/priv.h | 1 +
>   2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/nvkm/subdev/pwr/base.c b/nvkm/subdev/pwr/base.c
> index 0ab55f27ec45..1ea433a5e118 100644
> --- a/nvkm/subdev/pwr/base.c
> +++ b/nvkm/subdev/pwr/base.c
> @@ -26,7 +26,7 @@
>   
>   #include "priv.h"
>   
> -static void
> +void
>   nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
>   {
>   	const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr);
> diff --git a/nvkm/subdev/pwr/priv.h b/nvkm/subdev/pwr/priv.h
> index 3814a341db32..86149d9a440c 100644
> --- a/nvkm/subdev/pwr/priv.h
> +++ b/nvkm/subdev/pwr/priv.h
> @@ -26,6 +26,7 @@ int _nouveau_pwr_ctor(struct nouveau_object *, struct
nouveau_object *,
>   #define _nouveau_pwr_dtor _nouveau_subdev_dtor
>   int _nouveau_pwr_init(struct nouveau_object *);
>   int _nouveau_pwr_fini(struct nouveau_object *, bool);
> +void nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable);
>   
>   struct nvkm_pwr_impl {
>   	struct nouveau_oclass base;

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Hello Ben and Martin,

Any comments for this series?

Thanks,
Vince

On 12/22/2014 05:11 PM, Vince Hsu wrote:
> There might be some callers of nouveau_clock_astate(), and they are from
> inetrrupt context. So we must ensure that this function can be atomic in
> that condition. This patch adds one parameter which is subsequently passed
> to nouveau_pstate_calc(). Therefore we can choose whether we want to wait
> for the pstate work's completion or not.
>
> Signed-off-by: Vince Hsu <vinceh at nvidia.com>
> ---
>
> v2: none. (v1 is the RFC actually)
>
>   nvkm/include/subdev/clock.h | 2 +-
>   nvkm/subdev/clock/base.c    | 4 ++--
>   2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/nvkm/include/subdev/clock.h b/nvkm/include/subdev/clock.h
> index 36ed035d4d42..6c36f0e4385b 100644
> --- a/nvkm/include/subdev/clock.h
> +++ b/nvkm/include/subdev/clock.h
> @@ -159,7 +159,7 @@ int nva3_clock_pll_calc(struct nouveau_clock *, struct
nvbios_pll *,
>   			int clk, struct nouveau_pll_vals *);
>   
>   int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr);
> -int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
> +int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool
wait);
>   int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
>   int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
>   
> diff --git a/nvkm/subdev/clock/base.c b/nvkm/subdev/clock/base.c
> index e51b72d47129..b1bbe764fa35 100644
> --- a/nvkm/subdev/clock/base.c
> +++ b/nvkm/subdev/clock/base.c
> @@ -430,13 +430,13 @@ nouveau_clock_ustate(struct nouveau_clock *clk, int
req, int pwr)
>   }
>   
>   int
> -nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
> +nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool
wait)
>   {
>   	if (!rel) clk->astate  = req;
>   	if ( rel) clk->astate += rel;
>   	clk->astate = min(clk->astate, clk->state_nr - 1);
>   	clk->astate = max(clk->astate, 0);
> -	return nouveau_pstate_calc(clk, true);
> +	return nouveau_pstate_calc(clk, wait);
>   }
>   
>   int

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confidential information.  Any unauthorized review, use, disclosure or
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On Wed, Jan 7, 2015 at 3:10 PM, Vince Hsu <vinceh at nvidia.com>
wrote:
> Hello Ben and Martin,
>
> Any comments for this series?
Hey Vince,

Ah sorry, I thought my comment on the other patch indicated I was fine
with it.  I'll merge them now so they don't get lost :)

Thanks,
Ben.
>
> Thanks,
> Vince
>
>
> On 12/22/2014 05:11 PM, Vince Hsu wrote:
>>
>> There might be some callers of nouveau_clock_astate(), and they are
from
>> inetrrupt context. So we must ensure that this function can be atomic
in
>> that condition. This patch adds one parameter which is subsequently
passed
>> to nouveau_pstate_calc(). Therefore we can choose whether we want to
wait
>> for the pstate work's completion or not.
>>
>> Signed-off-by: Vince Hsu <vinceh at nvidia.com>
>> ---
>>
>> v2: none. (v1 is the RFC actually)
>>
>>   nvkm/include/subdev/clock.h | 2 +-
>>   nvkm/subdev/clock/base.c    | 4 ++--
>>   2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/nvkm/include/subdev/clock.h b/nvkm/include/subdev/clock.h
>> index 36ed035d4d42..6c36f0e4385b 100644
>> --- a/nvkm/include/subdev/clock.h
>> +++ b/nvkm/include/subdev/clock.h
>> @@ -159,7 +159,7 @@ int nva3_clock_pll_calc(struct nouveau_clock *,
struct
>> nvbios_pll *,
>>                         int clk, struct nouveau_pll_vals *);
>>     int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr);
>> -int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
>> +int nouveau_clock_astate(struct nouveau_clock *, int req, int rel,
bool
>> wait);
>>   int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
>>   int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
>>   diff --git a/nvkm/subdev/clock/base.c b/nvkm/subdev/clock/base.c
>> index e51b72d47129..b1bbe764fa35 100644
>> --- a/nvkm/subdev/clock/base.c
>> +++ b/nvkm/subdev/clock/base.c
>> @@ -430,13 +430,13 @@ nouveau_clock_ustate(struct nouveau_clock *clk,
int
>> req, int pwr)
>>   }
>>     int
>> -nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
>> +nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool
>> wait)
>>   {
>>         if (!rel) clk->astate  = req;
>>         if ( rel) clk->astate += rel;
>>         clk->astate = min(clk->astate, clk->state_nr - 1);
>>         clk->astate = max(clk->astate, 0);
>> -       return nouveau_pstate_calc(clk, true);
>> +       return nouveau_pstate_calc(clk, wait);
>>   }
>>     int
>
>
>
>
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On 07/01/15 07:10, Vince Hsu wrote:
> Hello Ben and Martin,
>
> Any comments for this series?
>
> Thanks,
> Vince
Hello Vince,

I have not really settled yet, so I don't think I have the time to 
review your patches right now as I have more urgent personnal priorities.

Sorry, hope to be available soon!

Martin