search for: nouveau_bo_wr32

.../drivers/gpu/drm/nouveau/nv84_fence.c index 7b372a68aa4e..4138db4d8291 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -120,6 +120,7 @@ nv84_fence_context_del(struct nouveau_channel *chan) nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); } + nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); nouveau_bo_vma_del(priv->bo, &fctx->vma_gart); nouveau_bo_vma_del(priv->bo, &fctx->vma); nouveau_fence_context_del(&fctx->base); @@ -159,8 +160,6 @@ nv84_fence_context_new(struct nouveau_channel *chan)...

...d != NULL; @@ -177,10 +178,11 @@ nvc0_fence_resume(struct nouveau_drm *drm) struct nouveau_fifo *pfifo = nouveau_fifo(drm->device); struct nvc0_fence_priv *priv = drm->fence; int i; + u32 chan = pfifo->max + 1; if (priv->suspend) { - for (i = 0; i <= pfifo->max; i++) - nouveau_bo_wr32(priv->bo, i, priv->suspend[i]); + for (i = 0; i < chan; i++) + nouveau_bo_wr32(priv->bo, i * 16/4, priv->suspend[i]); vfree(priv->suspend); priv->suspend = NULL; }

...-122,8 +122,11 @@ nv84_fence_context_del(struct nouveau_channel *chan) struct drm_device *dev = chan->drm->dev; struct nv84_fence_priv *priv = chan->drm->fence; struct nv84_fence_chan *fctx = chan->fence; + struct nouveau_fifo_chan *fifo = (void *)chan->object; int i; + nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, fctx->base.sequence); + for (i = 0; i < dev->mode_config.num_crtc; i++) { struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); @@ -168,7 +171,7 @@ nv84_fence_context_new(struct nouveau_channel...

...ds of the clock with the log-entries and they match - always) ============================================================================ Apr 29 22:16:06 h kernel: [ 78.633151] BUG: unable to handle kernel paging request at f84c8000 Apr 29 22:16:06 h kernel: [ 78.633265] IP: [<f8fb6be9>] nouveau_bo_wr32+0x29/0x60 [nouveau] Apr 29 22:16:06 h kernel: [ 78.633430] *pdpt = 0000000001b79001 *pde = 0000000034c88067 *pte = 0000000000000000 Apr 29 22:16:06 h kernel: [ 78.633546] Oops: 0002 [#1] SMP Apr 29 22:16:06 h kernel: [ 78.633596] Modules linked in: ctr ccm rfcomm bnep snd_hda_codec_realtek...

Revised patch set v2. [PATCH 1/8] drm/nouveau: bo read/write wrappers for nv04_crtc.c [PATCH 2/8] drm/nouveau: use bo accessors for push buffers [PATCH 3/8] drm/nouveau: OUT_RINGp - optimize OUT_RING loops [PATCH 4/8] drm/nv50: proper notifier_bo access in nv50_display_vblank_crtc_handler() [PATCH 5/8] drm/nouveau: access fbcon notifier via bo accessors [PATCH 6/8] drm/nouveau: screen_base and

...[ 14.072435] [<c10b6e4b>] ? create_object+0x1fa/0x207 [ 14.072443] [<c101d464>] ioremap_wc+0x1e/0x28 [ 14.072455] [<f81a19d0>] ? ttm_mem_reg_ioremap+0x70/0x93 [ttm] [ 14.072467] [<f81a19d0>] ttm_mem_reg_ioremap+0x70/0x93 [ttm] [ 14.072498] [<f8217588>] ? nouveau_bo_wr32+0x3ab/0x735 [nouveau] [ 14.072510] [<f81a1f74>] ttm_bo_move_memcpy+0x63/0x257 [ttm] [ 14.072528] [<f8163619>] ? drm_mm_put_block+0x161/0x228 [drm] [ 14.072538] [<c10b3130>] ? kmem_cache_alloc_notrace+0xa5/0xb1 [ 14.072555] [<f8163807>] ? drm_mm_add_space_to_tail+...

...7ae7f97..0619c02 100644 --- a/drivers/gpu/drm/nouveau/nv10_fence.c +++ b/drivers/gpu/drm/nouveau/nv10_fence.c @@ -162,6 +162,13 @@ nv10_fence_destroy(struct nouveau_drm *drm) kfree(priv); } +void nv17_fence_resume(struct nouveau_drm *drm) +{ + struct nv10_fence_priv *priv = drm->fence; + + nouveau_bo_wr32(priv->bo, 0, priv->sequence); +} + int nv10_fence_create(struct nouveau_drm *drm) { @@ -197,6 +204,8 @@ nv10_fence_create(struct nouveau_drm *drm) if (ret == 0) { nouveau_bo_wr32(priv->bo, 0x000, 0x00000000); priv->base.sync = nv17_fence_sync; + + priv->base.resume =...

...bool no_prefetch) { struct nvif_user *user = &chan->drm->client.device.user; struct nouveau_bo *pb = chan->push.buffer; int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; BUG_ON(chan->dma.ib_free < 1); + WARN_ON(length > NV50_DMA_PUSH_MAX_LENGTH); nouveau_bo_wr32(pb, ip++, lower_32_bits(offset)); - nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8); + nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8 | + (no_prefetch ? (1 << 31) : 0)); chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;...

...han->drm->client.device.user; > struct nouveau_bo *pb = chan->push.buffer; > int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; > > BUG_ON(chan->dma.ib_free < 1); > + WARN_ON(length > NV50_DMA_PUSH_MAX_LENGTH); > > nouveau_bo_wr32(pb, ip++, lower_32_bits(offset)); > - nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8); > + nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8 | > + (prefetch ? 0 : (1 << 31))); > It feels a bit weird to be in...

...gt;kmap); } +u32 +nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) +{ + bool is_iomem; + u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); + mem = &mem[index]; + if (is_iomem) + return ioread32_native((void __force __iomem *)mem); + else + return *mem; +} + +void +nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) +{ + bool is_iomem; + u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); + mem = &mem[index]; + if (is_iomem) + iowrite32_native(val, (void __force __iomem *)mem); + else + *mem = val; +} static struct ttm_backend * nouveau_...

..., + bool prefetch) { struct nvif_user *user = &chan->drm->client.device.user; struct nouveau_bo *pb = chan->push.buffer; int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; BUG_ON(chan->dma.ib_free < 1); + WARN_ON(length > NV50_DMA_PUSH_MAX_LENGTH); nouveau_bo_wr32(pb, ip++, lower_32_bits(offset)); - nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8); + nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8 | + (prefetch ? 0 : (1 << 31))); chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max; d...

...uct drm_device *dev, spin_lock(&nvbo->bo.lock); ret = ttm_bo_wait(&nvbo->bo, false, false, false); + spin_unlock(&nvbo->bo.lock); if (ret) { NV_ERROR(dev, "reloc wait_idle failed: %d\n", ret); break; } - spin_unlock(&nvbo->bo.lock); nouveau_bo_wr32(nvbo, r->reloc_bo_offset >> 2, data); } -- 1.6.6.1.476.g01ddb

...n) > struct drm_device *dev = chan->drm->dev; > struct nv84_fence_priv *priv = chan->drm->fence; > struct nv84_fence_chan *fctx = chan->fence; > + struct nouveau_fifo_chan *fifo = (void *)chan->object; > int i; > > + nouveau_bo_wr32(priv->bo, fifo->chid * 16/4, fctx->base.sequence); > + > for (i = 0; i < dev->mode_config.num_crtc; i++) { > struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); > nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); > @@ -168,...

...t; index 7b372a68aa4e..4138db4d8291 100644 > --- a/drivers/gpu/drm/nouveau/nv84_fence.c > +++ b/drivers/gpu/drm/nouveau/nv84_fence.c > @@ -120,6 +120,7 @@ nv84_fence_context_del(struct nouveau_channel *chan) > nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); > } > > + nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); > nouveau_bo_vma_del(priv->bo, &fctx->vma_gart); > nouveau_bo_vma_del(priv->bo, &fctx->vma); > nouveau_fence_context_del(&fctx->base); > @@ -159,8 +160,6 @@ nv84_fence_context_new(struct nouve...

...ouveau_bo *nvbo, unsigned index, u16 val) > mem = &mem[index]; > if (is_iomem) > iowrite16_native(val, (void __force __iomem *)mem); > - else > + else { > *mem = val; > + nv_cpu_cache_flush_area(mem, 2); > + } > } > > u32 > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) > mem = &mem[index]; > if (is_iomem) > iowrite32_native(val, (void __force __iomem *)mem); > - else > + else { > *mem = val; > + nv_cpu_cache_flush_area(mem, 4); > + } This looks rather like a sledgehammer to...

...*ref = NULL; + uint32_t offset = 0; + + nouveau_fence_update(kchan); + + if (nouveau_gpuobj_ref_find(chan, NvNotify1, &ref)) + return -ENOENT; + + if (nouveau_notifier_offset(ref->gpuobj, &offset)) + return -EINVAL; + + if (sequence > kchan->fence.sequence_ack) /* not done */ + nouveau_bo_wr32(chan->notifier_bo, offset >> 2, 0x22222222); + else /* done */ + nouveau_bo_wr32(chan->notifier_bo, offset >> 2, 0x11111111); + + return 0; +} + +int +nouveau_fence_semaphore_flush(struct nouveau_channel *chan, int channel) +{ + struct drm_device *dev = chan->dev; + struct drm...

...t;> --- a/drivers/gpu/drm/nouveau/nv84_fence.c >> +++ b/drivers/gpu/drm/nouveau/nv84_fence.c >> @@ -120,6 +120,7 @@ nv84_fence_context_del(struct nouveau_channel *chan) >> nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); >> } >> >> + nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); >> nouveau_bo_vma_del(priv->bo, &fctx->vma_gart); >> nouveau_bo_vma_del(priv->bo, &fctx->vma); >> nouveau_fence_context_del(&fctx->base); >> @@ -159,8 +160,6 @@ nv84_fe...

...c(size); if (!mem) return ERR_PTR(-ENOMEM); - if (DRM_COPY_FROM_USER(mem, userptr, nmemb * size)) { - kfree(mem); + if (DRM_COPY_FROM_USER(mem, userptr, size)) { + u_free(mem); return ERR_PTR(-EFAULT); } @@ -681,7 +697,7 @@ nouveau_gem_pushbuf_reloc_apply(struct nouveau_cli *cli, nouveau_bo_wr32(nvbo, r->reloc_bo_offset >> 2, data); } - kfree(reloc); + u_free(reloc); return ret; } @@ -743,7 +759,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, bo = u_memcpya(req->buffers, req->nr_buffers, sizeof(*bo)); if (IS_ERR(bo)) { - kfree(push); + u_f...

...t; > iowrite16_native(val, (void __force __iomem *)mem); > > > - else > > > + else { > > > *mem = val; > > > + nv_cpu_cache_flush_area(mem, 2); > > > + } > > > } > > > > > > u32 > > > @@ -461,8 +463,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) > > > mem = &mem[index]; > > > if (is_iomem) > > > iowrite32_native(val, (void __force __iomem *)mem); > > > - else > > > + else { > > > *mem = val; > > > + nv_cpu_cache_f...

- Depth and stencil buffers are supposed to be large enough in general. Signed-off-by: Maarten Maathuis <madman2003 at gmail.com> --- drivers/gpu/drm/nouveau/nouveau_bo.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index e342a41..9fc4bd6 100644 ---