Displaying 20 results from an estimated 25 matches for "noitinerary".
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2011 Dec 16
2
[LLVMdev] Typos in ARMInstrInfo.td ?
Hi,
I think there are a set of typos in the ATOMIC_LOAD_UMIN_I* and
ATOMIC_LOAD_UMAX_I*
pseudo-instructions .
Specifically,
def ATOMIC_LOAD_MIN_I32 : PseudoInst<
(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
[(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
and
def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
(outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
[(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
both reference a...
2011 Dec 21
0
[LLVMdev] Typos in ARMInstrInfo.td ?
...eorge Russell wrote:
> Hi,
>
> I think there are a set of typos in the ATOMIC_LOAD_UMIN_I* and
> ATOMIC_LOAD_UMAX_I*
> pseudo-instructions .
>
> Specifically,
>
> def ATOMIC_LOAD_MIN_I32 : PseudoInst<
> (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
> [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
>
> and
>
> def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
> (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
> [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GP...
2011 Dec 21
1
[LLVMdev] Typos in ARMInstrInfo.td ?
...t;>
>> I think there are a set of typos in the ATOMIC_LOAD_UMIN_I* and
>> ATOMIC_LOAD_UMAX_I*
>> pseudo-instructions .
>>
>> Specifically,
>>
>> def ATOMIC_LOAD_MIN_I32 : PseudoInst<
>> (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
>> [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
>>
>> and
>>
>> def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
>> (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
>> [(set GPR:$dst, (at...
2016 Dec 03
2
Immediate operand for vector instructions
...for the Mips back end):
class MSA_I16_FMT<bits<9> opcode>: MSAInst {
bits<16> s16;
let Inst{31-23} = opcode;
let Inst{26-11} = s16;
}
class REP_1R_DESC_BASE<,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
/* From include/llvm/Target/Target.td:
let OperandType = "OPERAND_IMMEDIATE" in {
...
def i64imm : Operand<i64>; */
dag InOperandList = (ins i64imm:$imm);
stri...
2017 Jul 24
2
How to lower a 'Store' node using the list<dag> pattern.
...(outs SURegisterOperand:$RegB),
[],
"movsuto_su\t$RegA,$RegB","RR",
[(store (i16 SURegisterOperand:$RegA), i16:$RegB)], NoItinerary>
{
bits<9> RegA;
bits<9> RegB;
let Inst{19-11} = RegA;
let Inst{...
2016 Mar 18
2
Immediate operand for load instruction, in back end
...ad class has $addrsrc which is a relative address with base a certain
register and offset:
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = mem_msa,
ComplexPattern Addr = addrimm10,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins MemOpnd:$addrsrc);
string AsmString = !strconcat("mov $wd, ($addrsrc)");
list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))];
InstrItinClass Itinerary = itin;
string DecoderMetho...
2014 Mar 03
2
[LLVMdev] Lower CFI IDs Using Target Intrinsic
...pattern. I admit that I don’t fully grok the tablegen syntax, so a lot of what I’ve been doing is trial and error, and based on examples in other *.td files.
Here’s what I think I’m shooting for...
/* Code in Target/ARM/ARMInstrInfo.td */
def ARMCFIID : AXI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary,
"cfiid", "\t$opt", [(int_arm_cfiid i32imm:$opt)]>,
Requires<[IsARM]> {
bits<32> opt;
let Inst{31-0} = opt;
}
...
I realize this is very wrong, but just to give you an idea of what I’m trying to do… basically take the i32 param...
2016 Oct 24
2
Instruction selection confusion at register - chooses vector register instead of scalar one
.... This is why I defined
the vector store like:
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst);
string AsmString = !strconcat("LS[$addrdst] = $wd;",
instr_asm);
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addrdst)];...
2014 Aug 05
2
[LLVMdev] Concerning not relevant argument count in TableGen Patterns.
...nstruction definition in the
TargetInstrInfo.td file should be like:
at first I am defining the class form my instruction:
*class Mymov<bits<6> op, string instr_asm>: FI<op, (outs Regs1:$rs),
(ins Regs2:$rt),
!strconcat(instr_asm, "\t$rt, $rs"),
[], NoItinerary> {
let imm16 = 0;
}*
where *Regs1* and *Regs2* are corresponding *RegisterClasses*.
Then I need to define the instruction:
*def MOVInstr : Mymov<0x2, "mov">;*
*def : TargetPat<(int_myintrinsicname), (MOVInstr)>;* /// error: In
anonymous.4: Instruction 'MOVInstr...
2017 Jul 27
2
Are there some strong naming conventions in TableGen?
...(outs ),
[],
"movsuto_a\t$ImmA,$OffsetB","I32O",
[(store (i16 IMM16Operand:$ImmA), FPUaOffsetOperand:$OffsetB)],NoItinerary>;
While building CLPGenDAGISel.inc, I got the following error:
-------------------------------------------------------------------------------------------------
Unknown leaf kind: IMM16Operand:i16:$ImmA
...
#7 0x00000000005210a1 (anonymous namespace)::MatcherGen::EmitLeafMatchCode(llvm::TreePat...
2017 Sep 20
1
Store lowering -> Cannot select FrameIndex.
...FPUaRegisterOperand:$RegB),
(outs ),
[],
"movsuto_a\t$ImmA,$RegB",
[(store i32:$ImmA, i16:$RegB)],NoItinerary> {
The selection DAG seems to be correct, but a FrameIndex of 0 as been introduced :
Optimized legalized selection DAG: BB#0 'storeloadi32:'
SelectionDAG has 6 nodes:
t0: ch = EntryToken
t5: ch = store<Volatile ST4[%ptr]> t0, Constant:i32<12>, FrameIndex:i16<0...
2016 Oct 25
0
Instruction selection confusion at register - chooses vector register instead of scalar one
...e. This is why I defined
the vector store like:
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst);
string AsmString = !strconcat("LS[$addrdst] = $wd;",
instr_asm);
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addrdst)];...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...class LD_INDIRECT_DESC_BASE2<string instr_asm,
ValueType TyNode,
RegisterOperand ROWD,
RegisterOperand ROWSI = ROWD,
RegisterOperand ROWSP = ROWD, // passthru register
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, ROWSI:$wsptr, ROWSI:$wsi);
string AsmString = "$wd = LS[R($wsi )];";
list<dag> Pattern = [(set ROWD:$wd, (TyNode (masked_gather ROWSP:$wsp, VK128Opnd
:$wsm,...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...dr", [],[SDNPWantParent]>;
>
> class LD_INDIRECT_DESC_BASE2<string instr_asm,
> RegisterOperand ROWD,
> RegisterOperand ROWSP = ROWD,
> InstrItinClass itin = NoItinerary> {
> dag OutOperandList = (outs ROWD:$wd, VK128Opnd:$wdm);
> dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, vx256xmem:$wsi);
> string AsmString = !strconcat("$wd = LS[$wsi]; // iread (or Mips MSA's LD)
> strinstr_asm = ",
>...
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...[], [RFLAGA],
"# OR_A_oo",
[(set FPUaROUTADDRegisterClass:$FA_ROUTADD,(or FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB))],NoItinerary>
{let usesCustomInserter = 1;}
The instructions selection and registers allocation are performed with the pseudo.
%4:fpuaoffsetclass = LOAD_A_r @a; FPUaOffsetClass:%4
%5:fpuaoffsetclass = LOAD_A_r @b; FPUaOffsetCla...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
..."selectVectorAddr", [],[SDNPWantParent]>;
class LD_INDIRECT_DESC_BASE2<string instr_asm,
RegisterOperand ROWD,
RegisterOperand ROWSP = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd, VK128Opnd:$wdm);
dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, vx256xmem:$wsi);
string AsmString = !strconcat("$wd = LS[$wsi]; // iread (or Mips MSA's LD)
strinstr_asm = ",...
2013 May 17
0
[LLVMdev] How to get rid of "xxx not a recognized feature for this target" warning?
Hello LLVMer,
I am currently developing a backend targeting a stack-based VM,
When compiling with targeting to the VM, I got a bunch of outputs below.
Where in code do I miss to add to get rid of these warnings?
'-sse4a' is not a recognized feature for this target (ignoring feature)
'-avx2' is not a recognized feature for this target (ignoring feature)
'-xop' is not a
2016 Dec 06
0
Immediate operand for vector instructions
Hi Alex,
On 5 December 2016 at 18:00, Alex Susu <alex.e.susu at gmail.com> wrote:
> We can compile it. Note that this is the only compilable code w.r.t.
> using i64 or i64imm (in the 2 lines above: "dag InOperandList", "list<dag>
> Pattern").
Yeah, you actually want to use "imm":
list<dag> Pattern = [(int_repeat_x_times imm:$imm)];
2016 Mar 22
0
Immediate operand for load instruction, in back end
...elative address with base a
> certain
> register and offset:
> class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
> ValueType TyNode, RegisterOperand ROWD,
> Operand MemOpnd = mem_msa,
> ComplexPattern Addr = addrimm10,
> InstrItinClass itin = NoItinerary> {
> dag OutOperandList = (outs ROWD:$wd);
> dag InOperandList = (ins MemOpnd:$addrsrc);
> string AsmString = !strconcat("mov $wd, ($addrsrc)");
> list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))];
> InstrItinClass Itinerary = iti...
2017 Feb 11
2
Specify special cases of delay slots in the back end
...- CreateTargetPostRAHazardRecognizer() to register the
[Target]DispatchGroupSBHazardRecognizer()
- insertNoop() which returns the target's NOP
- note that my vector (and scalar) instructions are inspired from the Mips back
end, which has MSAInst (and MipsInst) with NoItinerary InstrItinClass. Currently I am not
using a [Target]Schedule.td specifying functional units, processor and instruction
itineraries. This might be a problem - I guess ScoreboardHazardRecognizer relies on this
information.
In principle, should I maybe use the post-RA MI-scheduler instead of t...