search for: mulq

...15 pushq %r14 pushq %r13 pushq %r12 pushq %rbx movq %rdx, %rcx movq %rdi, -16(%rsp) # 8-byte Spill movq (%rsi), %rdi movq 8(%rsi), %r8 movq 8(%rcx), %rax movq %rax, -24(%rsp) # 8-byte Spill movq 16(%rcx), %rax movq %rax, -8(%rsp) # 8-byte Spill movq %rdi, %rax mulq -24(%rsp) # 8-byte Folded Reload You'll note that rbx,r12,r13,r14,r15,rbp are all dead after the pushes. But the spill code still insists on using rax to load the spilled values, forcing them to be reloaded later. Is the register allocator (pbqp, I think) capable of having values...

...age? It would be nice to be able to write all the code in C and compile it with Clang... but I need 256-bit integer support. (2) Is there a way to convince LLVM's register allocator to do the right thing on x86? I'm getting swaths of code like: movq 88(%rsp), %rax mulq 112(%rsp) movq %rax, %r15 addq %r11, %r15 movq %rdx, %r14 adcq %rcx, %r14 adcq $0, %r9 (that's a 64x64 -> 128-bit multiply with 192-bit accumulate.) The problem is, %r11 and %rcx are dead here. It should have just added %rax...

...ill >        movq    (%rsi), %rdi >        movq    8(%rsi), %r8 >        movq    8(%rcx), %rax >        movq    %rax, -24(%rsp)         # 8-byte Spill >        movq    16(%rcx), %rax >        movq    %rax, -8(%rsp)          # 8-byte Spill >        movq    %rdi, %rax >        mulq    -24(%rsp)               # 8-byte Folded Reload > > You'll note that rbx,r12,r13,r14,r15,rbp are all dead after the > pushes. But the spill code still insists on using rax to load the > spilled values, forcing them to be reloaded later. I'm not the most familiar with this sor...

...o compute the value. - */ - - while (1) { - u64 tmp; - u32 sequence = tsc_pg->tsc_sequence; - u64 cur_tsc; - u64 scale = tsc_pg->tsc_scale; - s64 offset = tsc_pg->tsc_offset; - - rdtscll(cur_tsc); - /* current_tick = ((cur_tsc *scale) >> 64) + offset */ - asm("mulq %3" - : "=d" (current_tick), "=a" (tmp) - : "a" (cur_tsc), "r" (scale)); - - current_tick += offset; - if (tsc_pg->tsc_sequence == sequence) - return current_tick; - - if (tsc_pg->tsc_sequence != 0) - continue; - /* - * Fallb...

On Wed, Feb 8, 2017 at 9:07 AM, Vitaly Kuznetsov <vkuznets at redhat.com> wrote: > Hyper-V TSC page clocksource is suitable for vDSO, however, the protocol > defined by the hypervisor is different from VCLOCK_PVCLOCK. Implement the > required support re-using pvclock_page VVAR as VCLOCK_PVCLOCK is mutually > exclusive with VCLOCK_HVCLOCK at run time. > > Signed-off-by:

On Wed, Feb 8, 2017 at 9:07 AM, Vitaly Kuznetsov <vkuznets at redhat.com> wrote: > Hyper-V TSC page clocksource is suitable for vDSO, however, the protocol > defined by the hypervisor is different from VCLOCK_PVCLOCK. Implement the > required support re-using pvclock_page VVAR as VCLOCK_PVCLOCK is mutually > exclusive with VCLOCK_HVCLOCK at run time. > > Signed-off-by:

Hi, merge window is about to close so I hope it's OK to make another try here. Changes since v2: - Add explicit READ_ONCE() to not rely on 'volatile' [Andy Lutomirski] - rdtsc() -> rdtsc_ordered() [Andy Lutomirski] - virt_rmb() -> smp_rmb() [Thomas Gleixner, Andy Lutomirski] Thomas, Andy, it seems the only blocker for the series was the ambiguity with TSC page read algorithm.

Hi, merge window is about to close so I hope it's OK to make another try here. Changes since v2: - Add explicit READ_ONCE() to not rely on 'volatile' [Andy Lutomirski] - rdtsc() -> rdtsc_ordered() [Andy Lutomirski] - virt_rmb() -> smp_rmb() [Thomas Gleixner, Andy Lutomirski] Thomas, Andy, it seems the only blocker for the series was the ambiguity with TSC page read algorithm.

Hi, while we're still waiting for a definitive ACK from Microsoft that the algorithm is good for SMP case (as we can't prevent the code in vdso from migrating between CPUs) I'd like to send v2 with some modifications to keep the discussion going. Changes since v1: - Document the TSC page reading protocol [Thomas Gleixner]. - Separate the TSC page reading code from

Hi, while we're still waiting for a definitive ACK from Microsoft that the algorithm is good for SMP case (as we can't prevent the code in vdso from migrating between CPUs) I'd like to send v2 with some modifications to keep the discussion going. Changes since v1: - Document the TSC page reading protocol [Thomas Gleixner]. - Separate the TSC page reading code from

...t; +; ATOM: cwtl >> } >> >> declare i1 @return_false() >> @@ -256,8 +256,8 @@ entry: >> %call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone >> ret i8* %call >> ; CHECK-LABEL: test12: >> -; CHECK: movq $-1, %[[R:r..]] >> ; CHECK: mulq >> +; CHECK: movq $-1, %[[R:r..]] >> ; CHECK: cmovnoq %rax, %[[R]] >> ; CHECK: jmp __Znam >> >> >> Modified: llvm/trunk/test/CodeGen/X86/shift-bmi2.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-bmi2.ll?rev=192750...