search for: mul

...; preds = %L0, %L1 %2 = phi i64 [ %arg0, %L1 ], [ %0, %L0 ] %3 = phi i64 [ %arg1, %L1 ], [ %1, %L0 ] %4 = sdiv i64 %2, 4 %5 = sdiv i64 %3, 4 br label %L5 L3: ; preds = %L7, %L5 %6 = phi i64 [ %528, %L7 ], [ 0, %L5 ] %7 = mul i64 %527, 4 %8 = add nsw i64 %7, %6 %9 = mul i64 %527, 1 %10 = add nsw i64 %9, 0 %11 = mul i64 %10, 9 %12 = add nsw i64 %11, 0 %13 = mul i64 %12, 2 %14 = add nsw i64 %13, 0 %15 = mul i64 %14, 4 %16 = add nsw i64 %15, %6 %17 = mul i64 %527, 4 %18 = add nsw i64 %17, %...

...%2 = phi i64 [ %arg0, %L1 ], [ %0, %L0 ] > %3 = phi i64 [ %arg1, %L1 ], [ %1, %L0 ] > %4 = sdiv i64 %2, 4 > %5 = sdiv i64 %3, 4 > br label %L5 > > L3: ; preds = %L7, %L5 > %6 = phi i64 [ %528, %L7 ], [ 0, %L5 ] > %7 = mul i64 %527, 4 > %8 = add nsw i64 %7, %6 > %9 = mul i64 %527, 1 > %10 = add nsw i64 %9, 0 > %11 = mul i64 %10, 9 > %12 = add nsw i64 %11, 0 > %13 = mul i64 %12, 2 > %14 = add nsw i64 %13, 0 > %15 = mul i64 %14, 4 > %16 = add nsw i64 %15, %6 > %17 = mul...

...0, %L0 ] >> %3 = phi i64 [ %arg1, %L1 ], [ %1, %L0 ] >> %4 = sdiv i64 %2, 4 >> %5 = sdiv i64 %3, 4 >> br label %L5 >> >> L3: ; preds = %L7, %L5 >> %6 = phi i64 [ %528, %L7 ], [ 0, %L5 ] >> %7 = mul i64 %527, 4 >> %8 = add nsw i64 %7, %6 >> %9 = mul i64 %527, 1 >> %10 = add nsw i64 %9, 0 >> %11 = mul i64 %10, 9 >> %12 = add nsw i64 %11, 0 >> %13 = mul i64 %12, 2 >> %14 = add nsw i64 %13, 0 >> %15 = mul i64 %14, 4 >> %16 =...

Hi Renato, you are right! There is 'avx' support: fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 x2apic popcnt aes xsave avx lahf_lm ida arat epb xsaveopt pln pts dts tpr_shadow vnmi flexpriority ept vpid This is still strange: Why is this the only IR where 256 bit vectors are found and for all other functions...

I'll try to run through the scenario: 64-bit register type target (all registers have 64 bits). all 32-bits are getting promoted to 64-bit integers Problem: MUL on i32 is getting promoted to MUL on i64 MUL on i64 is getting expanded to a library call in compiler-rt the problem is that MUL32 gets promoted and then converted into a subroutine call because it is now type i64, even though I want the MUL I32 to remain as an operation in the architecture. MU...

...o obtain VM incremental data，and use virsh blockcommit，qemu-img commit，qemu-img rebase to shorten snapshot chain. Details are as follows（when VM running state， we perform the following operations）: (1) the host machine control VM test virsh snapshot-create-as mix snap1 --diskspec vda,file=/tmp/mul/loop-mix-commit-rebase/snap1-mix.img --disk-only --atomic --quiesce virsh snapshot-create-as mix snap2 --diskspec vda,file=/tmp/mul/loop-mix-commit-rebase/snap2-mix.img --disk-only --atomic --quiesce virsh snapshot-create-as mix snap3 --diskspec vda,file=/tmp/mul/loop-mix-commit-rebase/snap3-mix.im...

On Saturday, March 4, 2017, Ryan Taylor <ryta1203 at gmail.com> wrote: > Why you can't still expand it through MUL with a Custom lowering? Or am I > missing something? > > Yes we can but problem occurs when we know that it is shift with constant value than if we return ISD::MUL with constant imm operand than LLVM will convert it to SHL again because the constant will be power of 2. Thus it creates loop...

On Tue, Jul 30, 2013 at 01:14:16PM -0600, Dan wrote: > I'll try to run through the scenario: > > > 64-bit register type target (all registers have 64 bits). > > all 32-bits are getting promoted to 64-bit integers > > Problem: > > MUL on i32 is getting promoted to MUL on i64 > > MUL on i64 is getting expanded to a library call in compiler-rt > > Can you fix this by marking i64 MUL as Legal? > the problem is that MUL32 gets promoted and then converted into a > subroutine call because it is now type i64, eve...

...main... BBV: found 0 instructions with candidate pairs BBV: done! BBV: fusing loop #1 for for.body10 in main... BBV: found 22 instructions with candidate pairs BBV: found 82 pair connections. BBV: selected pairs in the best tree for: %0 = load i8* %r.063, align 1, !tbaa !0 BBV: selected pair: %mul23 = mul nsw i32 %conv14, 234 <-> %mul35 = mul nsw i32 %conv15, 543 BBV: selected pair: %0 = load i8* %r.063, align 1, !tbaa !0 <-> %1 = load i8* %incdec.ptr11, align 1, !tbaa !0 BBV: selected pair: %conv14 = zext i8 %0 to i32 <-> %conv15 = zext i8 %1 to i32 BBV: selected...

Hi, On Fri, Dec 30, 2011 at 3:09 AM, Tobias Grosser <tobias at grosser.es> wrote: > As it seems my intuition is wrong, I am very eager to see and understand > an example where a search limit of 4000 is really needed. > To make the ball roll again, I attached a testcase that can be tuned to understand the impact on compile time for different sizes of a basic block. One can also

On Sat, Mar 4, 2017 at 1:19 PM, Bruce Hoult <bruce at hoult.org> wrote: > If your target does not have SHL then why don't you simply disable > converting MUL to SHL? > > MUL is converted to SHL by target independent passes when second operand is power of 2. -Vivek > > On Sat, Mar 4, 2017 at 8:22 AM, vivek pandya via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> >> On Saturday, March 4, 2017, Ryan Tay...

On Thu, 2012-01-26 at 15:12 -0600, Sebastian Pop wrote: > On Thu, Jan 26, 2012 at 2:49 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > Thanks! Did you compile with any non-default flags other than -mllvm > > -vectorize? > > I used -O3 and -vectorize, no other non-default flags. If I run clang -O3 -mllvm -vectorize -S -emit-llvm -o test.ll test.c then I get no

On 12/29/2011 06:32 PM, Hal Finkel wrote: > On Thu, 2011-12-29 at 15:00 +0100, Tobias Grosser wrote: >> On 12/14/2011 01:25 AM, Hal Finkel wrote: >> One thing that I would still like to have is a test case where >> bb-vectorize-search-limit is needed to avoid exponential compile time >> growth and another test case that is not optimized, if >>

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/shader/Makefile | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/shader/Makefile b/src/shader/Makefile index 46658e9..2d789be 100644 --- a/src/shader/Makefile +++ b/src/shader/Makefile @@ -24,20 +24,21 @@ NVF0_SHADERS = xfrm2nvf0.vpc \ videonvf0.fpc SHADERS = $(NVC0_SHADERS)

Hello LLVM Devs, I am working on a target on which no SHL instruction is available. So wanted to expand it through MUL. But currently it is only possible to expand SHL for vector types. One possible reason I can think is because LLVM tries to optimize MUL to SHL in certain cases and that can make compiler co in loop or may end up generating wrong code. But I think SHL should be able to expanded to MUL and to prev...

Hi everyone! I use the libvirt(version: 1.2.2) and QEMU(version: 2.2.1) to test qemu snapshot features: I tried virsh blockcommit when VM offline, the virsh blockcommit failed: the error messase as below: error: Requested operation is not valid: domain is not running when I start the VM, the virsh blockcommit work fine! my question is：we need

...0, 0.5000, 300.0000} IMM[5] FLT32 { 0.2000, 0.0300, 8.0000, 100.0000} IMM[6] FLT32 { 450.0000, 1.5000, 0.2500, 1.0500} IMM[7] FLT32 { 1.3333, 1.4427, 5.0000, 0.0000} 0: MOV TEMP[0], IN[0] 1: MAD TEMP[0].y, IN[0], CONST[19].zzzz, CONST[19].wwww 2: MUL TEMP[1].x, CONST[4].xxxx, IMM[0].xxxx 3: MOV TEMP[2].xyz, -CONST[0].xyzx 4: ADD TEMP[3].xyz, CONST[2].xyzz, -IN[5].xyzz 5: DP3 TEMP[4].x, TEMP[3].xyzz, TEMP[3].xyzz 6: RSQ TEMP[4].x, TEMP[4].xxxx 7: MUL TEMP[3].xyz, TEMP[3].xyzz, TEMP[4].xxxx 8: ADD TEMP[4].xyz, TEMP[2].xyzz, TEMP[3].xy...

Hi all, I have been looking at the way LLVM optimizes code before forwarding it to the backend I develop for my company and while building define i32 @test_extract_subreg_func(i32 %x, i32 %y) #0 { entry: %conv = zext i32 %x to i64 %conv1 = zext i32 %y to i64 %mul = mul nuw i64 %conv1, %conv %shr = lshr i64 %mul, 32 %xor = xor i64 %shr, %mul %conv2 = trunc i64 %xor to i32 ret i32 %conv2 } I came upon the following optimization (during instcombine): *IC: Visiting: %mul = mul nuw i64 %conv, %conv1 IC: Visiting: %shr = lshr i64 %mul, 32 IC: Vis...

...o treat "undef" as a SNaN for "fdiv". The question is whether we can make the same assumption for other floating point operations, or "fdiv" needs a correction to prevent folding since signalling of SNaNs might be disabled. >> /InstructionSimplify folds "mul %X, undef" to 0 always/ Sorry, I malformed this line and forgot to highlight that by "%X" I meant a constant here. So, constant folding comes into play. The result depends on the constant parity. E.g.: mul i64 5, undef --> undef mul i64 4, undef --> 0 I still have d...

...the combination of nsw flag and ExtLdPromotion, I am leaning to say Clang set nsw flag incorrectly, but please let me know if I was wrong. Here is the reduced testcase: long long foo(int *a) { long long c; c = *a * 1405; return c; } Clang emitted the following IR (It is done by EmitMUL() in CGExprScalar.cpp, while CGF.getLangOpts().getSignedOverflowBehavior()=LangOptions::SOB_Undefined and CGF.SanOpts.has(SanitizerKind::SignedIntegerOverflow)=false): ; Function Attrs: nounwind readonly define i64 @foo(i32* nocapture readonly %a) #0 { entry: %0 = load i32* %a, align 4, !t...