Displaying 20 results from an estimated 22 matches for "msix_entries_nr".
2009 Jun 02
0
[PATCHv2 05/13] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->mask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 02
0
[PATCHv2 05/13] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->mask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 18
0
[PATCHv5 05/13] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 18
0
[PATCHv5 05/13] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 10
0
[PATCHv4 05/13] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 10
0
[PATCHv4 05/13] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 May 25
1
[PATCH 05/11] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->mask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 May 25
1
[PATCH 05/11] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->mask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 21
1
[PATCHv6 05/12] qemu/pci: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 21
1
[PATCHv6 05/12] qemu/pci: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 05
1
[PATCHv3 05/13] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2009 Jun 05
1
[PATCHv3 05/13] qemu: MSI-X support functions
...bar_nr);
+ pdev->msix_cap = config_offset;
+ /* Make flags bit writeable. */
+ pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
+ return 0;
+}
+
+static void msix_free_irq_entries(PCIDevice *dev)
+{
+ int vector;
+
+ for (vector = 0; vector < dev->msix_entries_nr; ++vector)
+ dev->msix_entry_used[vector] = 0;
+}
+
+/* Handle MSI-X capability config write. */
+void msix_write_config(PCIDevice *dev, uint32_t addr,
+ uint32_t val, int len)
+{
+ unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
+ if (addr + len &...
2011 Nov 02
3
[PATCH RFC 0/2] virtio-pci: polling mode support
MSIX spec requires that device can be operated with
all vectors masked, by polling.
So the following patchset (lightly tested) adds this
ability: when driver reads ISR, the device
recalls a pending notification, and returns
pending status in the ISR register.
The polling driver can operate as follows:
- map all VQs and config to the same vector
- poll ISR to get status - this also flushes VQ
2011 Nov 02
3
[PATCH RFC 0/2] virtio-pci: polling mode support
MSIX spec requires that device can be operated with
all vectors masked, by polling.
So the following patchset (lightly tested) adds this
ability: when driver reads ISR, the device
recalls a pending notification, and returns
pending status in the ISR register.
The polling driver can operate as follows:
- map all VQs and config to the same vector
- poll ISR to get status - this also flushes VQ
2009 Aug 13
0
[PATCHv2 3/3] qemu-kvm: vhost-net implementation
..._config(PCIDevice *pci_dev, uint32_t address,
msix_write_config(pci_dev, address, val, len);
}
+static int virtio_pci_irqfd(void * opaque, uint16_t vector, int fd)
+{
+ VirtIOPCIProxy *proxy = opaque;
+ struct kvm_irqfd call = { };
+ int r;
+
+ if (vector >= proxy->pci_dev.msix_entries_nr)
+ return -EINVAL;
+ if (!proxy->pci_dev.msix_entry_used[vector])
+ return -ENOENT;
+ call.fd = fd;
+ call.gsi = proxy->pci_dev.msix_irq_entries[vector].gsi;
+ r = kvm_vm_ioctl(kvm_state, KVM_IRQFD, &call);
+ if (r < 0)
+ return r;
+ return 0;
+}...
2009 Aug 13
0
[PATCHv2 3/3] qemu-kvm: vhost-net implementation
..._config(PCIDevice *pci_dev, uint32_t address,
msix_write_config(pci_dev, address, val, len);
}
+static int virtio_pci_irqfd(void * opaque, uint16_t vector, int fd)
+{
+ VirtIOPCIProxy *proxy = opaque;
+ struct kvm_irqfd call = { };
+ int r;
+
+ if (vector >= proxy->pci_dev.msix_entries_nr)
+ return -EINVAL;
+ if (!proxy->pci_dev.msix_entry_used[vector])
+ return -ENOENT;
+ call.fd = fd;
+ call.gsi = proxy->pci_dev.msix_irq_entries[vector].gsi;
+ r = kvm_vm_ioctl(kvm_state, KVM_IRQFD, &call);
+ if (r < 0)
+ return r;
+ return 0;
+}...
2009 Aug 17
1
[PATCHv3 3/4] qemu-kvm: vhost-net implementation
..._config(PCIDevice *pci_dev, uint32_t address,
msix_write_config(pci_dev, address, val, len);
}
+static int virtio_pci_irqfd(void * opaque, uint16_t vector, int fd)
+{
+ VirtIOPCIProxy *proxy = opaque;
+ struct kvm_irqfd call = { };
+ int r;
+
+ if (vector >= proxy->pci_dev.msix_entries_nr)
+ return -EINVAL;
+ if (!proxy->pci_dev.msix_entry_used[vector])
+ return -ENOENT;
+ call.fd = fd;
+ call.gsi = proxy->pci_dev.msix_irq_entries[vector].gsi;
+ r = kvm_vm_ioctl(kvm_state, KVM_IRQFD, &call);
+ if (r < 0)
+ return r;
+ return 0;
+}...
2009 Aug 17
1
[PATCHv3 3/4] qemu-kvm: vhost-net implementation
..._config(PCIDevice *pci_dev, uint32_t address,
msix_write_config(pci_dev, address, val, len);
}
+static int virtio_pci_irqfd(void * opaque, uint16_t vector, int fd)
+{
+ VirtIOPCIProxy *proxy = opaque;
+ struct kvm_irqfd call = { };
+ int r;
+
+ if (vector >= proxy->pci_dev.msix_entries_nr)
+ return -EINVAL;
+ if (!proxy->pci_dev.msix_entry_used[vector])
+ return -ENOENT;
+ call.fd = fd;
+ call.gsi = proxy->pci_dev.msix_irq_entries[vector].gsi;
+ r = kvm_vm_ioctl(kvm_state, KVM_IRQFD, &call);
+ if (r < 0)
+ return r;
+ return 0;
+}...
2009 Aug 10
0
[PATCH 3/3] qemu-kvm: vhost-net implementation
..._config(PCIDevice *pci_dev, uint32_t address,
msix_write_config(pci_dev, address, val, len);
}
+static int virtio_pci_irqfd(void * opaque, uint16_t vector, int fd)
+{
+ VirtIOPCIProxy *proxy = opaque;
+ struct kvm_irqfd call = { };
+ int r;
+
+ if (vector >= proxy->pci_dev.msix_entries_nr)
+ return -EINVAL;
+ if (!proxy->pci_dev.msix_entry_used[vector])
+ return -ENOENT;
+ call.fd = fd;
+ call.gsi = proxy->pci_dev.msix_irq_entries[vector].gsi;
+ r = kvm_vm_ioctl(kvm_state, KVM_IRQFD, &call);
+ if (r < 0)
+ return r;
+ return 0;
+}...
2009 Aug 10
0
[PATCH 3/3] qemu-kvm: vhost-net implementation
..._config(PCIDevice *pci_dev, uint32_t address,
msix_write_config(pci_dev, address, val, len);
}
+static int virtio_pci_irqfd(void * opaque, uint16_t vector, int fd)
+{
+ VirtIOPCIProxy *proxy = opaque;
+ struct kvm_irqfd call = { };
+ int r;
+
+ if (vector >= proxy->pci_dev.msix_entries_nr)
+ return -EINVAL;
+ if (!proxy->pci_dev.msix_entry_used[vector])
+ return -ENOENT;
+ call.fd = fd;
+ call.gsi = proxy->pci_dev.msix_irq_entries[vector].gsi;
+ r = kvm_vm_ioctl(kvm_state, KVM_IRQFD, &call);
+ if (r < 0)
+ return r;
+ return 0;
+}...