search for: mri

Hi there! I have two date columns in a dataframe I need to selectively collapse based on missing values and which date comes first (imported from an text file). This is what I did: RHSSP$CT <- as.POSIXct(RHSSP$CT, format='%m/%d/%y %H:%M') RHSSP$MRI <- as.POSIXct(RHSSP$MRI, format='%m/%d/%y %H:%M') RHSSP$Scan <- ifelse(is.na(RHSSP$MRI),RHSSP$CT,ifelse(is.na(RHSSP$CT),RHSSP$MRI,ifelse(RHSSP$CT>RHSSP$MRI,RHSSP$MRI,RHSSP$CT))) RHSSP$CT and RHSSP$MRI remain properly formatted (e.g.: "2011-06-21 22:31:00 PDT") BUT...

On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: > So if this early exit is taken: > > // SSA defs do not have output/anti dependencies. > // The current operand is a def, so we have at least one. > if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) > return; > > we do not ever get to this point: > > VRegDefs.insert(VReg2SUnit(Reg, SU)); > > But later, when checking for anti dependency for another MI here: > > void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperId...

...different return-value registers than normal return instructions. See PR14750 for the details. To fix this, I am going to remove the live-out lists from MachineRegisterInfo. These functions are going to be removed: - addLiveOut() - liveout_begin() - liveout_end() - isLiveOut() Instead of calling MRI.addLiveOut(), targets should add return value registers as implicit operands on return instructions. This is already how argument registers are passed to call instructions, making calls and returns work the same way. I'll be updating the in-tree targets. Other targets need to make three change...

...void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { const MachineInstr *MI = SU->getInstr(); unsigned Reg = MI->getOperand(OperIdx).getReg(); // SSA defs do not have output/anti dependencies. // The current operand is a def, so we have at least one. if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) <<<<<<<<<<<<<<<<<< This is what I am missing. See below. return; // Add output dependence to the next nearest def of this vreg. // // Unless this definition is dead, the output dependence should be...

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>

...LivePhysRegs for each basic block in a function. The function then loops through all instructions in a basic block and checks to see if it is a dead instruction. The check is whether it is a physical register or not with the check: TargetRegisterInfo::isPhysicalRegister(reg) ? LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg) If the register is virtual, then MRI->use_nodbg_empty() returns false, if the register is physical LivePhysRegs[Reg] returns false, since the bitvector was inverted. So my instruction is considered dead and deleted. So, what I am trying to figure out is why this behavi...

Hi, I wanted to see the non-debug uses of register 0 (Noreg) and so, I wrote the following piece of code. ***** MRI = &MF.getRegInfo(); if (!MRI->use_nodbg_empty(0)) { for (MachineRegisterInfo::use_nodbg_iterator ri = MRI->use_nodbg_begin(0), re = MRI->use_nodbg_end(); ri != re; ++ri) { MachineInstr *UseMI = &*ri; UseMI->dump (); } } ***** But...

...39;t convert a register to a class. In fact there's not always a single or canonical class for a given register. What is the right way to do this? unsigned SrcReg = Reg + VA.getValNo(); unsigned DestReg = VA.getLocReg(); // Avoid a cross-class copy. This is very unlikely. if (!MRI.getRegClass(SrcReg)->contains(DestReg)) return false; ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160923/3927db50/attachment.html>

...s for each basic block in a function. The function then loops through all instructions in a basic block and checks to see if it is a dead instruction. The check is whether it is a physical register or not with the check: > > TargetRegisterInfo::isPhysicalRegister(reg) ? LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg) > > If the register is virtual, then MRI->use_nodbg_empty() returns false, if the register is physical LivePhysRegs[Reg] returns false, since the bitvector was inverted. So my instruction is considered dead and deleted. > Huh? The code is if (TargetRe...

...sync samba information / Password using the field userPassword that contains the hash for unix password ? Thanks for reading me, Olivier. ________ Example of old account imported with "smbldap-populate dump.ldif" ( missing all samba information ! ) : dn: uid=charrasse,ou=Users,dc=mri.cnrs,dc=fr loginShell: /bin/bash sn: Charrasse objectClass: top,inetOrgPerson,posixAccount,mri-user gidNumber: 513 accountType: user status: active mail: sophie.charrasse@BLAH.fr givenName: Sophie uid: charrasse uidNumber: 1583 cn: charrasse userPassword: {MD5}c+URcajBLAHDcSObg== homeDirectory: /ho...

Dale, Yeah that is correct, so that isn't the problem, not sure why I was thinking it is. The !MRI->use_no_dbg_empty(Reg) seems to be correct and the problem is LivePhysRegs[Reg] always returning false. I've looked into this more and there is a part where I'm working with physical registers. If there is a function call, there is a copy from virtual register space to the functions that...

...: [LLVMdev] Assert in live update from MI scheduler. On Jun 13, 2012, at 10:49 AM, Sergei Larin <slarin at codeaurora.org> wrote: So if this early exit is taken: // SSA defs do not have output/anti dependencies. // The current operand is a def, so we have at least one. if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) return; we do not ever get to this point: VRegDefs.insert(VReg2SUnit(Reg, SU)); But later, when checking for anti dependency for another MI here: void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { ... // Add antidependence to the follow...

...arget = TargetRegistry::lookupTarget(TripleName, Error); if (!TheTarget) { std::cerr << "llvm_insts_to_binary(): " << Error; return 1; } Then, I move on to creating some of the needed ASM / REG info and an MCContext, etc.: std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); assert(MRI && "Unable to create target register info!"); std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName)); assert(MAI && "Unable to create target asm info!"); std::string MCP...

Andy, Thanks for reply. I was able to trace the problem to the MI DAG dep constructor. See this: SU(0): %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10 # preds left : 0 # succs left : 0 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 SU(1): %vreg10<def> = LDriw %vreg9<kill>, 0;

Hey all, I've found a bug in either the PBQP register allocator or in VirtRegRewriter. I'm observing this assertion in VirtRegRewriter::rewrite() fail: unsigned VirtReg = MO.getReg(); unsigned PhysReg = VRM->getPhys(VirtReg); ... assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); Indeed there is a case where PhysReg may be a reserved physical register. Specificially, RegAllocPBQP::finalizeAlloc() may select a physical register thusly: const TargetRegisterClass &RC = *MRI.getRegClass(L...

Hello, We''ve been migrating our fairly large Rails 1.2 application from MRI 1.8.6 to REE 1.8.7, and in the process we''ve encountered some fairly odd behavior. Namely, instead of the expected reduction in memory usage, we''re seeing an increase in memory usage by around 40% and, along with it, an increase in processor usage. The stock 1.8.7 implementat...

Heya all, Anyone have any ideas on this one? http://rubyforge.org/tracker/index.php?func=detail&aid=13825&group_id=85&atid=411 It''s easy enough to rescue, I''d just like to know what MRI does in this case, so we can duplicate it. Regards, Dan

...#39;s the best way to get alias and mod-ref info without having two alias calls. A couple of ideas: (a) Extend the getModRefInfo interface (+getModRefBehavior, +gerArgModRefInfo) to return a pair {ModRefInfo, AliasResult}. The AliasResult can be optional based on an argument e.g.: struct MRI_AR { ModRefInfo MRI, AliasResult AR }; MRI_AR getModRefInfoAlias (LoadInst *LI, MemoryLocation Loc, bool SetAliasResultField); Add wrapper APIs to preserve current calls. e.g.: ModRefInfo getModRefInfo (LoadInst *LI, MemoryLocation Loc) { return getModRefInfoAlias (LI, Loc,...

...otIndex OldIdx) { SlotIndex LastUse = NewIdx; if (TargetRegisterInfo::isPhysicalRegister(Reg)) { for (MCRegUnitRootIterator Roots(Reg, &TRI); Roots.isValid(); ++Roots) { unsigned Root = *Roots; for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Root), UE = MRI.use_nodbg_end(); UI != UE; UI.skipInstruction()) { const MachineInstr* MI = &*UI; SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI); if (InstSlot > LastUse && InstSlot &lt...

We''ve run into this before and, in this particular project, I''m positive we had a hack somewhere to get AR to work but it seems to have gone missing and I''m not finding any hints in git history or Google. Any call to an AR.create will trigger it. Seems like a strategically placed require or include did the trick but I''m probably misremembering. The offending