search for: mi

...peat stepwise selection, then record how many times variables are chosen by step() in bootstrap replications. When I use step() (or stepAIC) to do model selection, I got errors. Here is the part of my code for (j in 1:mm){ #<--mm=10 for (b in 1:nrow(reg.bs)){ #<--bootstrap 10 times mi<-data.frame(tlfup,cen,complete(imp,j)) #<--completed data sets after MI in.star<-sample(1:n,n,replace=T) #<--to sample id number 1-1851. data.star<-mi[in.star,] M<-coxph(Surv(tlfup,cen)~mi$trt+mi$nodes+mi$htypeed1+mi$htypeed2+mi$ngra ded2+mi$agem40 +mi$agem40sq+mi$er+mi$pr,da...

Thank you for Prof.Ripley's suggestion. I fixed the program by adding a lower scope, and the program ran, but I still got warning messages, and don't know what is going on, would this affect my results? ... Step: AIC= 12337.74 Surv(tlfup, cen) ~ MI[[j]]$trt + MI[[j]]$agem40 + MI[[j]]$agem40sq + mhtypeed1 + mhtypeed2 Df AIC <none> 12338 - MI[[j]]$agem40sq 1 12338 - MI[[j]]$agem40 1 12339 - mhtypeed2 1 12353 - mhtypeed1 1 12365 There were 50 or more warnings (use warnings() t...

On Dec 2, 2011, at 12:40 PM, Evan Cheng wrote: > ---------------- > | Bundle * | (A MI with special opcode "Bundle") > ---------------- > | > ---------------- > | MI * | > ---------------- > | >...

...olio.optim with 3 assets, without the asset with weight equals to zero, it returns a completely different result. That's I would expected the same weights as the run with 4 assets. Below the code. Thanks in advance, Alberto Santini ------------------------------------- require(tseries) f.mi <- coredata(get.hist.quote("F.MI", start="2006-09-03", compression="w", quote="Close")) eng.mi <- coredata(get.hist.quote("ENG.MI", start="2006-09-03", compression="w", quote="Close")) tis.mi <- coredata(get.hi...

. and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier.. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Friday, December 02,...

Machine Instruction Bundle in LLVM Hi all, There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community. Design Criteria 1. The bundle representation must be light weight. We cannot afford to add significant memory or compile time overhead. 2. It must be flexible enough to rep...

...on as.numeric(), pero me toca hacerlo variable por variable: >Base$Variable1<-as.numeric( Base$Variable1) >Base$Variable2<-as.numeric( Base$Variable2) etcétera, el problema es que tengo muchas variables y no puedo hacer esto una por una. Por esto vengo aquí a buscar una idea o asesoramiento. Gracias. [[alternative HTML version deleted]]

On Dec 2, 2011, at 2:41 PM, Sergei Larin wrote: > … and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier…. Isn't that just the order of the instructions in the list? I don't see anything that prevents getting the order of instructions. It might require iterator over MIs in the packet. But for targets lik...

Evan, I will need to comprehend it better, but one small comment right away. Did we not discuss one more option for bundle implementation - global cycle ID. We would add an unsigned int field to MI definition representing "global scheduling cycle". All MIs with the same global cycle value belong to one group/packet. Zero means unscheduled MI. That is light weight, position independent (means if instructions are added/reordered by a pass that does not care for packets/groups,...

...just read your proposal and the following discussion for VLIW support and want to share my experience of writing a VLIW back-end for LLVM. I would not integrate the packetizer into the register allocator super class since it would reduce the flexibility for the back-end developer to add some optimization passes after the packetizer. Instead, I would add the packetizer as a separate pass. It is true that the packetizer must deal in that case with PHI and COPY nodes that are eliminated by the RA. The packetizer can simple group all PHI and COPY instruction into single bundles consisting of only...

On Thu, Jun 27, 2013 at 9:50 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > On Jun 26, 2013, at 4:18 PM, Eric Christopher <echristo at gmail.com> wrote: > > > So inverting it so that MI contains LLVM IR instead of the other way > > around? Then we'd need a serialization format for MI that happened to > > include a way of serializing LLVM IR within. From a quick "hey, this > > seems reasonable" the idea of embedding the MI into the IR rather than &gt...

With a modified copy of LLVM (so it's probably my fault) I'm getting an assertion failure because isTwoAddrUse (in TwoAddressInstructionPass.cpp) is being called with a MachineInstr MI such that MI.getNumOperands() is 2, but MI.getDesc().getNumOperands() is 5. The assertion fails when that function calls MI.getOperand(2). My question is: is isTwoAddrUse doing the right thing here? static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { const Targe...

Dear R-experts, I am struggling with the following problem, and I am looking for advice from more experienced R-users: I have a data frame with 2 identifying variables (comn and mi), and an output variable (x). comn is a variable for a company and mi is a variable for a month. comn<-c("abc", "abc", "abc", "abc", "abc", "abc", "xyz", "xyz","xyz", "xyz") mi<- c("1&quo...

..., at 10:12 AM, Chandler Carruth <chandlerc at google.com> wrote: > > On Thu, Jun 27, 2013 at 9:50 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > On Jun 26, 2013, at 4:18 PM, Eric Christopher <echristo at gmail.com> wrote: > > > So inverting it so that MI contains LLVM IR instead of the other way > > around? Then we'd need a serialization format for MI that happened to > > include a way of serializing LLVM IR within. From a quick "hey, this > > seems reasonable" the idea of embedding the MI into the IR rather than &gt...

Hello! I get the following message when I run the mi() function from the mi package. Error while imputing variable: c3 , model: mi.polr Error in eval(expr, envir, enclos) : could not find function "c14ordered" Here's the situation: I am running R v. 2.9.2 on Mac OSX v. 10.5.8. I am trying to impute missing data in a data set...

Dear R experts, I have a problem in modifying one column of a dataframe with a datatime format using a datetime operator. Here is my dataframe A: DATACONT PROVINCIA VALORE 1 2007-12-31 MI 1 2 2007-12-31 PV 2 3 2007-12-31 NA 3 4 2007-12-31 MI 4 5 2007-12-31 RM 5 6 2007-12-31 RM 6 7 2007-12-31 MI 7 8 2008-12-31 MI 11 9 2008-12-31 PV 12 10 2008-12-31 NA 13 11 2008-12-31...

...ote: > OK, here's a new patch that adds the infrastructure and the > implementation for X86, ARM and PPC of GetInstSize and > GetFunctionSize. Both functions are virtual functions defined in > TargetInstrInfo.h. > > For X86, I moved some commodity functions from X86CodeEmitter to > X86InstrInfo. > > What do you think? > > Nicolas > > > Evan Cheng wrote: >> >> I think both of these belong to TargetInstrInfo. And yes, it's a >> good idea, there are other passes which can make use of them, e.g. >> branch shorte...

Full_Name: Claus Pastor Version: 2.9.2 OS: Windows XP Submission from: (NULL) (82.113.106.4) I use the following function to compute MutualInformation Matrix of factorial members of a dataframe. I use package minet for this: my.MI = function(test) { ## die Diagonale gibt die Entropien, Teile durch entropy von y und du erh?lst den Zusammenhang ## kenne X...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And yes, it's a good > idea, there are other passes which can make use of them, e.g. branch > shortening. > > Thanks, > > Evan > > &gt...

I would like to make a suggestion. In the LiveIntervalAnalysis class, instead of numbering the instructions in the order in which basic blocks are stored in the machine function, use the df_ext_iterator. It will order the instruction according to the dominance tree (or it seems to be doing so). There are many advantages in doing this. One of them is that, once you traverse the dominance tree to find the live intervals, they will be contiguous, you don't have to handle holes. Could someone tell me if there is any problem in doing this? In my...