search for: mi2

My CLEC just called and asked if we will support the "MI2" protocol on our proposed T1 circuit. I think this is for CallerID name. Will the T100P support this? Thanks, Mike

...'mlogit' package, 'Kenneth Train's exercises using the mlogit package for R.' In spite of using the code unchanged, as well as the data used in the examples, I have been unable to run a Wald test to test two models. Specifically, I have run the following command, where mc and mi2 are fitted models: waldtest(mc,mi2) I think that the test is taken from the 'lmtest' package. I get the following error message: Error in terms.default(x) : no terms component The two fitted models are: mc <- mlogit(depvar ~ ic + oc, H, reflevel="hp") mi2 <- mlogit(depvar...

Hi all, I am working on an out-of-tree target. I am wondering if it is possible to force the register allocator (and/or spiller) to not break certain instruction sequence. For example: phys_reg = MI1 vreg1 vreg 2 = MI2 phys_reg Is there a way to tell RA/spiller not to insert COPY or spill between MI1 and MI2? I am using greedy register allocator and inline spiller. -- Regards, Dongrui -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/a...

...o be handling insert locations inside bundles well. If the spill instruction is part of a bundle, the new DBG_VALUE is inserted after it, but does not have the bundling flags set. This essentially means that if we start with a set of bundled instructions: MI1 [BundledSucc=true, BundledPred=false] MI2 [BundledSucc=false, BundledPred=true] Where MI1 is a spill, and MI2 is a different instruction, after ExtendRanges we end up with MI1 [BundledSucc=true, BundledPred=false] DBG_VALUE MI [BundledSucc=false, BundledPred=false] MI2 [BundledSucc=false, BundledPred=true] Since this happens after the...

...o be handling insert locations inside bundles well. If the spill instruction is part of a bundle, the new DBG_VALUE is inserted after it, but does not have the bundling flags set. This essentially means that if we start with a set of bundled instructions: MI1 [BundledSucc=true, BundledPred=false] MI2 [BundledSucc=false, BundledPred=true] Where MI1 is a spill, and MI2 is a different instruction, after ExtendRanges we end up with MI1 [BundledSucc=true, BundledPred=false] DBG_VALUE MI [BundledSucc=false, BundledPred=false] MI2 [BundledSucc=false, BundledPred=true] Since this happens after the...

...$D, $t0):$MI1), (isScalarType type:$D), (isLargerType type:$D, type:$S)), (apply (G_ZEXT $D, $S, (debug_locations $MI0, $MI1)))>; def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1, instr:$MI2, instr:$MI3, debug_expr:$DNewExpr), (match (G_ZEXT $t0, $S):$MI0, (G_TRUNC $D, $t0):$MI1, (DBG_VALUE $t0):$MI2, (DBG_VALUE $D):$MI3, (isScalarType type...

...t; (match (G_ZEXT $t0, $S):$MI0, >> (G_TRUNC $D, $t0):$MI1), >> (isScalarType type:$D), >> (isLargerType type:$D, type:$S)), >> (apply (G_ZEXT $D, $S, (debug_locations $MI0, $MI1)))>; >> def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1, instr:$MI2, instr:$MI3, debug_expr:$DNewExpr), >> (match (G_ZEXT $t0, $S):$MI0, >> (G_TRUNC $D, $t0):$MI1, >> (DBG_VALUE $t0):$MI2, >> (DBG_VALUE $D):$MI3, >>...

MI2 starts ok but when I click new game it just kinda freezes, though the music keeps playing. Any ideas? last line is: wine: Unhandled page fault on read access to 0x7f0c3400 at address 0x68615040 (thread 0034), starting debugger... Could you post your .wine/user.reg ? the DllOverrides section?

...# Conjunto de riesgo. Número de observaciones mayores o iguales a cada valor # que toma la variable aleatoria (a cada y_j) r <- sort(cumsum(s), decreasing = TRUE) # Kernel gamma # Probabilidades discretas a suavizar p <- s/n # Parámetro de forma común de las distribuciones gamma mi2 <- sum(y**2*s) mi4 <- sum(y**4*s) alfa <- sqrt(n/(mi4/mi2 - 1)) # Función de distribución suavizada. Mixtura k-puntos con kernel gamma Keg <- function(x){sum(sapply(1:k, function(j){p[j]*pgamma(x, shape = alfa, scale = y[j]...

Hi, I'd like to submit a patch to match the clang patch on the front end. http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20140414/103257.html The front end doesn't need this patch to work but it's still important. This is mostly based on work done by kai from redstar.de Could I get some feedback on this? I'm not sure if the emitting of the register names will effect

Hi, I saw this setup on the web .. is this looks right to you ? The security set to user level, which use linux samba local login and password. Why this needs to set workgroup = SAMBAGRP ? [global] workgroup = SAMBAGRP security = user passdb backend = tdbsam Thanks

Hello everybody,, This time i want to replicate PDC to BDC when there's is any changes on PDC, here is my conf. on /etc/openldap/slapd.conf LDAP Server master moduleload syncprov overlay syncprov syncprov-checkpoint 100 10 syncprov-sessionlog 100 LDAP Server mirror moduleload syncprov syncrepl rid=001 provider=ldap://ldap.domain.com:389 bindmethod=simple

...r, the documentation about readsReg() states that a sub-register def implicitly reads the other parts of the register being redefined unless the <undef> flag is set. Now, I am writing a pass the splits the following sequence of MIs MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. MI2:: B<def> = C & A ; C and B are also 64bit super regs. Into NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg. NewMI_2:: B:hi_sub_reg<def> = 0 The question is how should I be setting up the <undef> flags on the def operands of NewMI_1 and 2 ? Should I set...

In order to implement a subtle memory access optimisation during post-RA scheduling, I want to be able to determine some properties about the memory access. If I have two registers referring to memory, how can I determine if they are derived from the same base-pointer? Often LLVM will optimise to use intermediate registers holding partial displacements, for example, when a 'struct'

...into a single range. However, this is not safe if A3 is a subreg define while A3 is not a subreg use. For instance, consider this code (part of a single block loop). MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, 2, // Post Inc. Load. Vreg7 is a 64bit reg. MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> // This is the A3 = B0 above. MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill> // Use the lo subreg that was setup in MI1: .... .... MI4:: %vreg32<def> = COPY %vreg7;...

Hi Dear ! I?m practice lab File server (SAMBA with CentOS 4.6), With model SAMBA is DOMAIN members of domain 2003 server (Sharing file and authenticate with account Domain 2003). I?m configure windbind (following document userguide): cp ../samba/source/nsswitch/libnss_winbind.so /lib ln -s /lib/libnss winbind.so /lib/libnss winbind.so.2 c?u h?nh /etc/nsswitch.conf # Cau

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation

...t;LM2" ,"LM3", "DB1" ,"DB2" ,"DB3", "DM1" , "DM2" , "DM3" , "FI1", "FI2", "BKI1", "BKI2", "BKO1", "BKO2", "BKO3", "SUR1","MI1","MI2","MI3","BHE1","BHE2","BHE3","BHW1","BHW2","BHW3","HAL1","HAL2","HAL3","HAL4","HAL5","HAL6","HAL7","DOH1","DOH2","DOH3",&quot...

...$S, (debug_locations $DL0, $DL1)))>; However, the former is more compact when DBG_VALUE is involved since naming the instruction gives access to three of the four pieces of data we need to pass on to the apply step: def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1, instr:$MI2, instr:$MI3, debug_expr:$DNewExpr), (match (G_ZEXT $t0, $S):$MI0, (G_TRUNC $D, $t0):$MI1, (DBG_VALUE $t0):$MI2, (DBG_VALUE $D):$MI3, (isScalarType type...

...() states that a sub-register > def implicitly reads the other parts of the register being redefined unless > the <undef> flag is set. > > Now, I am writing a pass the splits the following sequence of MIs > > MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. > MI2:: B<def> = C & A ; C and B are also 64bit super regs. > > Into > NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg. > NewMI_2:: B:hi_sub_reg<def> = 0 > > The question is how should I be setting up the <undef> flags on the def > opera...