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Forwarding to llvm-dev... ---------- Forwarded message ---------- From: Magnus Pettersson <mangepe at gmail.com> Date: Thu, Apr 14, 2011 at 21:33 Subject: Re: [LLVMdev] LLVM Scheduler and Itinieraries: Negative latency? To: Anton Korobeynikov <anton at korobeynikov.info> Hello Anton, I am trying to model a fairly simple five stage pipelined processor. The problem is that some instruct...

Hello, While trying to create back end in LLVM I have stumbled upon a problem I have trouble to get past, hopefully someone can give me hints on what I am doing wrong. The problem is that the assertion in the file ScheduleDAGList.cpp row 187 is triggered: "Negative latency". How does this happen? As background: My target has one issue unit, therefore my Schedule.td file only

Have not gotten much further on this, I can so far only use one memory with (for example) def LDr1 : F1< (outs GenRegs:$dst), (ins GenRegs:$addr), "ld*0* $dst, ($addr)", [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>; and def LDrr : F1< (outs GenRegs:$dst), (ins MEMrr:$addr), "ld*0* $dst, ($addr)",

Hello, My target has two data memories, each with its own load/store instructions but also has some instructions using both memories. I want to be able to access both memories in C-programs through the address space attribute. I have two ideas so far: Either: use two sets of addressing modes in InstrInfo.td: def ADDRrr_A : ComplexPattern<i16, 2, “SelectADDRrr_A", [], []>; def ADDRri :