search for: lowerintrinsic_wo_chain

...lue Op, SelectionDAG &DAG) const { > SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); > return LowerGlobalAddress(MFI, Op, DAG); > } > + case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG); > case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); > case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); > } > @@ -1680,6 +1687,40 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, > } > } > > +SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const &gt...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

...(i16, i16) #1 PromoteIntegerOperand Op #1: 0x33f090: i32 = llvm.opus.smuls 0x33f008, 0x33ee70, 0x33ef80 [ORD=4] [ID=0] Do not know how to promote this operator's operand! UNREACHABLE executed at ..\..\..\..\lib\CodeGen\SelectionDAG\LegalizeIntegerTypes.cpp:763! I've tried adding a custom LowerINTRINSIC_WO_CHAIN handler. What's the right way of doing this? Thanks, -Martin

Hi, I have some newly defined intrinsic functions in my llvm IR code, which I want to translate to X86 instruction set. As a first step, I want to be able to generate "nop" for these instructions, so the program at least compiles successfully. The call to my intrinsic function looks like this in the IR: call void @llvm.X(i16 %43) >From what I understand it may be possible to

...:UREM, MVT::i32, Expand); > +} > + > +SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) > + const > +{ > + switch (Op.getOpcode()) { > + default: return AMDILTargetLowering::LowerOperation(Op, DAG); > + case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); > + case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); > + case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); > + } > +} > + > +SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, > + SelectionDAG &DAG) const > +{ > + unsigned IntrinsicI...