llvm dev - May 2013 - [LLVMdev] backend for intrinsic functions

Hi,

I have some newly defined intrinsic functions in my llvm IR code, which I want
to translate to X86 instruction set. As a first step, I want to be able to
generate "nop" for these instructions, so the program at least
compiles successfully.

The call to my intrinsic function looks like this in the IR:
call void @llvm.X(i16 %43)
>From what I understand it may be possible to pattern match this to the nop
instructions in the backend. I did not find an example of intrinsic function
translation in the X86 backend. Could you explain how this can be done, or point
me to some places to look?
Thanks,
Ali

Hey Ali,

On Fri, May 17, 2013 at 3:46 PM, Ali Javadi <aj14889 at yahoo.com> wrote:
> Hi,
>
> I have some newly defined intrinsic functions in my llvm IR code, which I
> want to translate to X86 instruction set. As a first step, I want to be
> able to generate "nop" for these instructions, so the program at
least
> compiles successfully.
>
> The call to my intrinsic function looks like this in the IR:
> call void @llvm.X(i16 %43)
>
> From what I understand it may be possible to pattern match this to the nop
> instructions in the backend.

I would first attempt this in LowerINTRINSIC_WO_CHAIN(...)
from lib/Target/X86/X86ISelLowering.cpp. That may or may not be the right
way to go... just a thought.

> I did not find an example of intrinsic function translation in the X86
> backend. Could you explain how this can be done, or point me to some places
> to look?
>
As for matching intrinsics, check out lib/Target/X86/X86InstrSSE.td. For
example, here is a pattern that matches a 256 bit unaligned store intrinsic
to the AVX vmovups instruction.

def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
          (VMOVUPSYmr addr:$dst, VR256:$src)>;

-Cameron
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