search for: liveins

...t; index 266ebf6..fc787f2 100644 > --- a/lib/CodeGen/MachineRegisterInfo.cpp > +++ b/lib/CodeGen/MachineRegisterInfo.cpp > @@ -227,7 +227,9 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, > // complicated by the debug info code for arguments. > LiveIns.erase(LiveIns.begin() + i); > --i; --e; > - } else { > + //Make sure we don't emit the same livein copies twice, in case this > + //function is called more than once. > + } else if (def_empty(LiveIns[i].second)) { > // Emit a copy. &gt...

...deGen/MachineRegisterInfo.cpp > > > +++ b/lib/CodeGen/MachineRegisterInfo.cpp > > > @@ -227,7 +227,9 @@ > > MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, > > > // complicated by the debug info code for arguments. > > > LiveIns.erase(LiveIns.begin() + i); > > > --i; --e; > > > - } else { > > > + //Make sure we don't emit the same livein copies twice, in case > > this > > > + //function is called more than once. > > > + } else if (def_e...

...44 > > --- a/lib/CodeGen/MachineRegisterInfo.cpp > > +++ b/lib/CodeGen/MachineRegisterInfo.cpp > > @@ -227,7 +227,9 @@ > MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, > > // complicated by the debug info code for arguments. > > LiveIns.erase(LiveIns.begin() + i); > > --i; --e; > > - } else { > > + //Make sure we don't emit the same livein copies twice, in case > this > > + //function is called more than once. > > + } else if (def_empty(LiveIns[i].second)) { &gt...

Hi all, Is there a pass that computes livein information for each MachineBasicBlock? I tried to find such a pass but could not find any. I am trying to use the livein information to get dead registers to insert some instructions right before code emission but the livein information seems to be invalidated by some pass. I might need to recompute the livein information before my pass. Thanks a

....cpp > > > > +++ b/lib/CodeGen/MachineRegisterInfo.cpp > > > > @@ -227,7 +227,9 @@ > > > MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, > > > > // complicated by the debug info code for arguments. > > > > LiveIns.erase(LiveIns.begin() + i); > > > > --i; --e; > > > > - } else { > > > > + //Make sure we don't emit the same livein copies twice, in > case > > > this > > > > + //function is called more than once. > &gt...

I would like to maintain the livein information for physical registers on basic blocks past register allocation, or recreate it if possible. The goal is to be able to run a late pass of DeadMachineInstrElim, which requires valid livein information. The X86 target returns false for requiresRegisterScavenging so passes like BranchFolding don't update the livein information. At that point I

While beginning to add vector registers to a back end I came across the following problem: as soon as I define two sets of registers that have a many-to-one mapping the live interval pass appears to double- kill the mapped-onto register. I have the following excerpts from my RegisterInfo.td. def V4R0 : R4v<0 , "V4R0 ", []>, DwarfRegNum<0>; def R0 : Rg<0 ,

On Mar 25, 2007, at 7:12 AM, Christopher Lamb wrote: > While beginning to add vector registers to a back end I came across > the following problem: as soon as I define two sets of registers > that have a many-to-one mapping the live interval pass appears to > double-kill the mapped-onto register. I have the following excerpts > from my RegisterInfo.td. > > def V4R0

Thanks -- View this message in context: http://llvm.1065342.n5.nabble.com/is-liveIns-in-machineBasicBlock-only-valid-for-first-block-in-machine-function-tp63667.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

While migrating my codebase from llvm-2.6 to llvm-2.7, I found a different behaviour in the register allocation. I have been able to reproduce it using the msp430 backend, with the 2.7 release as well as the svn head. For the msp430, the first four parameters of a function are passed thru registers. What I observe is that if those parameters are not used inside the function, those registers can

...nd out why. Here is the beginning of the BB dump. entry (0x8503c80, LLVM BB @0x8501af0, ID#0): Live Ins: %R0 %R1 %reg1024 = ORI %R0<kill>, 0 %reg1025 = ORI %R1<kill>, 0 V4R0 is getting killed because handleLiveInRegister() is called on all results of getAliasSet() for each of the liveins (this is in LiveIntervals::computeIntervals() ). handleRegisterDef() does a similar thing where calls handlePhysicalRegisterDef() on all members of getAliasSet() returned for the def, which also triggers this problem. Is it calling handle*() on the alias set of a register thats the culpri...

Hi again, 2009/1/13 Evan Cheng <evan.cheng at apple.com>: > > > On Jan 13, 2009, at 12:27 AM, Roman Levenstein <romix.llvm at googlemail.com> > wrote: > >> 2009/1/13 Evan Cheng <echeng at apple.com>: >>> >>> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >>> >>>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1:

Adds code to have DCE start off with a list of physical registers to be live on entry to at least one successor basic block (as mentioned in the FIXME comment). -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: FIXME.patch Type: text/x-diff Size: 899 bytes Desc: not available URL:

On Jun 21, 2011, at 12:51 AM, Sanjoy Das wrote: > Adds code to have DCE start off with a list of physical registers to be > live on entry to at least one successor basic block (as mentioned in the > FIXME comment). Looks good, but keep the comment (sans FIXME).

2009/1/13 Evan Cheng <echeng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > >> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >> Predecessors according to CFG: 0x8fdac90 (#0) >> %R0<def> = MOVi 0, 14, %reg0, %reg0 >> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >> [0x8fc2d68 + 0]

On Jan 13, 2009, at 12:27 AM, Roman Levenstein <romix.llvm at googlemail.com > wrote: > 2009/1/13 Evan Cheng <echeng at apple.com>: >> >> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >> >>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>> Predecessors according to CFG: 0x8fdac90 (#0) >>> %R0<def> = MOVi 0, 14, %reg0,

On Jan 14, 2010, at 6:39 PM, 任坤 wrote: > But I want do some optimization after register alloction by adjusting > register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same

I'm having trouble with overlapping intervals for vector registers. How are intervals for registers that both alias to the same larger register intended to be handled? To demonstrate this problem you can use a minor addition to the Sparc register description. Add this to the SparcRegisterInfo.td at line 68: // Rtest class Rtest<bits<5> num, string n, list<Register>

Is there an easy way to obtain all liveout variables of a basic block? Liveins can be found for each MachineBasicBlock, but I can only find liveouts for the whole function, at MachineRegisterInfo. Do I need to find them out manually?

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's