search for: jalr

...) # 4-byte Folded Spill sw $17, 1652($sp) # 4-byte Folded Spill sw $16, 1648($sp) # 4-byte Folded Spill move $fp, $sp addu $17, $2, $25 lw $1, %got($main.a)($17) addiu $5, $1, %lo($main.a) lw $25, %call16(memcpy)($17) addiu $16, $fp, 1248 move $4, $16 addiu $6, $zero, 400 jalr $25 move $gp, $17 lw $1, %got($main.b)($17) addiu $5, $1, %lo($main.b) lw $25, %call16(memcpy)($17) addiu $17, $fp, 848 move $4, $17 jalr $25 addiu $6, $zero, 400 sw $zero, 820($fp) sw $zero, 844($fp) addiu $2, $fp, 420 b $BB0_2 addiu $3, $fp, 20 $BB0_1: -------------- next part -------------- An H...

...t sure if anyone is working on this already, any inputs are very welcome. I'm now looking at function calls which in the RISCV backend are represented via two pseudoinstructions RISCV::TAIL and RISCV::CALL. Currently those pseudos are lowered in MCCodeEmitter. They are expanded into AUIPC and JALR instructions and the first one needs a relocation, which for a static reloc model is R_RISCV_CALL but for PIC code should be R_RISCV_CALL_PLT. The problem I find is that at this point it is too late to tell the exact relocation needed: as far as I can tell there is no way to determine the relocati...

...$1, 0($3) lw $3, 56($sp) bne $1, $3, $BB0_8 lw $2, 40($sp) # BB#7: # %SP_return lw $ra, 60($sp) # 4-byte Folded Reload jr $ra addiu $sp, $sp, 64 $BB0_8: # %CallStackCheckFailBlk lw $25, %call16(__stack_chk_fail)($gp) jalr $25 nop .set at .set macro .set reorder .end _Z5sum_iiz $tmp4: .size _Z5sum_iiz, ($tmp4)-_Z5sum_iiz .cfi_endproc .globl main .align 2 .type main, at function .set nomips16 # @main .ent main main: .cfi_startproc .frame $sp,48,$ra .mask 0x80000000,-4 .fmask 0x00000000...

...$3, $BB0_8 > lw $2, 40($sp) > # BB#7: # %SP_return > lw $ra, 60($sp) # 4-byte Folded Reload > jr $ra > addiu $sp, $sp, 64 > $BB0_8: # %CallStackCheckFailBlk > lw $25, %call16(__stack_chk_fail)($gp) > jalr $25 > nop > .set at > .set macro > .set reorder > .end _Z5sum_iiz > $tmp4: > .size _Z5sum_iiz, ($tmp4)-_Z5sum_iiz > .cfi_endproc > > .globl main > .align 2 > .type main, at function > .set nomips16 # @main > .ent main > main: > .cfi_sta...

...ra,12(sp) 6: 06300793 li a5,99 a: 842a mv s0,a0 c: 00a7cb63 blt a5,a0,22 <.L2> 10: 85aa mv a1,a0 12: 00000537 lui a0,0x0 16: 00050513 mv a0,a0 1a: 00000317 auipc t1,0x0 1e: 000300e7 jalr t1 00000022 <.L2>: 22: 40b2 lw ra,12(sp) 24: 8522 mv a0,s0 26: 4422 lw s0,8(sp) 28: 0141 addi sp,sp,16 2a: 8082 ret And after linking: 00010164 <foo>: 10164: 1141 add...

Hi LLVM developers, Thank Daniel Sanders, Aditya Nandakumar and Justin Bogner's Tutorial[1]: Head First into GlobalISel about how to port, and Aditya took BPF target as a simple instance: bool BPFCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,                                   const Value *Val, unsigned VReg) const {   assert(!Val == !VReg && "Return value

...daddu $28,$28,$25 daddiu $28,$28,%lo(%neg(%gp_rel(main))) move $2,$4 sd $5,8($fp) sll $2,$2,0 sw $2,0($fp) ld $2,%got_page(.LC0)($28) daddiu $4,$2,%got_ofst(.LC0) ld $2,%call16(puts)($28) move $25,$2 .reloc 1f,R_MIPS_JALR,puts 1: jalr $25 nop move $2,$0 move $sp,$fp gslq $31,$fp,32($sp) ld $28,24($sp) daddiu $sp,$sp,48 j $31 nop .set macro .set reorder .end main .size main, .-main .ident "GCC: (GNU) 4.9.3 2...

...transformation and match them to my LISR & CALL instructions in my XXXInstrInfo.td TableGen file. I've been looking at how the Mips target has hi/lo relocations to handle 16-bits of an address at a time, but I don't see how the relocations are inserted(?) into the patterns for the JAL/JALR nodes. Does anyone have any advice on the best way to do this, and/or how the Mips addresses are handled? 2) I'm also not sure how (or at what stage of codegen) to check if the callee lives in the same instruction segment. How can I compare a call instruction's address with that of its t...

...a mv s0,a0 >> c: 00a7cb63 blt a5,a0,22 <.L2> >> 10: 85aa mv a1,a0 >> 12: 00000537 lui a0,0x0 >> 16: 00050513 mv a0,a0 >> 1a: 00000317 auipc t1,0x0 >> 1e: 000300e7 jalr t1 >> >> 00000022 <.L2>: >> 22: 40b2 lw ra,12(sp) >> 24: 8522 mv a0,s0 >> 26: 4422 lw s0,8(sp) >> 28: 0141 addi sp,sp,16 >> 2a: 8082 ret >> >> And af...

Which part of the generated code do you think is not correct? Could you be more specific? I compiled this program with clang and ran it on a mips board. It returns the expected result (21). On Tue, Feb 19, 2013 at 4:15 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I check the Mips backend for the following C code fragment compile result. > It seems not correct. Is it my

...offset 31, -4 $tmp4: .cfi_offset 18, -8 $tmp5: .cfi_offset 17, -12 $tmp6: .cfi_offset 16, -16 addu $16, $2, $25 move $17, $4 lw $18, %call16(foo)($16) $BB0_1: # %loop # =>This Inner Loop Header: Depth=1 move $25, $18 jalr $25 move $gp, $16 addiu $17, $17, -1 bnez $17, $BB0_1 nop # BB#2: # %exit lw $16, 16($sp) # 4-byte Folded Reload lw $17, 20($sp) # 4-byte Folded Reload lw $18, 24($sp) # 4-byte Folded Reload lw $ra, 28($sp) # 4-byte...

I check the Mips backend for the following C code fragment compile result. It seems not correct. Is it my misunderstand or it's a bug. //ch8_3.cpp #include <stdarg.h> int sum_i(int amount, ...) { int i = 0; int val = 0; int sum = 0; va_list vl; va_start(vl, amount); for (i = 0; i < amount; i++) { val = va_arg(vl, int); sum += val; } va_end(vl);

...e $sp,24,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat # BB#0: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -24 sw $ra, 20($sp) # 4-byte Folded Spill addu $gp, $2, $25 lw $1, %got($str)($gp) lw $25, %call16(puts)($gp) jalr $25 addiu $4, $1, %lo($str) addiu $2, $zero, 0 lw $ra, 20($sp) # 4-byte Folded Reload jr $ra addiu $sp, $sp, 24 .set at .set macro .set reorder .end main $tmp2: .size main, ($tmp2)-main .type $str, at object # @str .section .rodata.str1.4,"aMS", at progb...

I need to be able to emit .globl for the soft float routines used by mips16. The routines are called but there is no .globl definition for them. How can I do this? Background: I have a strange issue that I encountered with mips16 hard float. Part of mips16 hard float is to emit calls to runtime routines with the same signature as usual soft float routines, except that they are implemented

...;> move $2,$4 >> sd $5,8($fp) >> sll $2,$2,0 >> sw $2,0($fp) >> ld $2,%got_page(.LC0)($28) >> daddiu $4,$2,%got_ofst(.LC0) >> ld $2,%call16(puts)($28) >> move $25,$2 >> .reloc 1f,R_MIPS_JALR,puts >> 1: jalr $25 >> nop >> >> move $2,$0 >> move $sp,$fp >> gslq $31,$fp,32($sp) >> ld $28,24($sp) >> daddiu $sp,$sp,48 >> j $31 >> nop >> >> .set macro >&g...

Hi, Does lld support linker relaxation that may shrink code size? As far as I see lld seems to assume that the content of input sections to be fixed other than patching up relocations, but I believe some targets may benefit the extra optimization opportunity with relaxation. Specifically, I'm currently working on adding support for RISC-V in lld, and RISC-V heavily relies on linker relaxation

...en in the code above. If someone would help me figure out what goes > here, I would be very thankful: > SDValue Hi = ? > SDValue Lo = ? > > > > Is it possible to just emit a DMFC1 instruction with physical register operands? Something like this: (A0, A1) = DMFC1 vreg0 JALR T9, A0, A1 I think it's easier than trying to force or guide register allocator to assign successive even-odd i32 registers to DMFC1's destination registers. > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http:/...

...$2, %hi(_gp_disp) > addiu $2, $2, %lo(_gp_disp) > addiu $sp, $sp, -24 > sw $ra, 20($sp) # 4-byte Folded Spill > addu $gp, $2, $25 > lw $1, %got($str)($gp) > lw $25, %call16(puts)($gp) > jalr $25 > addiu $4, $1, %lo($str) > addiu $2, $zero, 0 > lw $ra, 20($sp) # 4-byte Folded Reload > jr $ra > addiu $sp, $sp, 24 > .set at > .set macro > .set reorder >...

I'm working on a target based on the MIPS target, and when I copy f64 values into 32 bit registers for calling functions, I need the operation to work on a of 32 bit registers (because the language I'm translating to isn't actually mips). I've been looking at how to do this, but I haven't been able to figure it out. Since the Mips target code is still really close to mine,

...# merge lowest "halfword" - - daddiu a0, sp, 64 # Pointer to ELF entry structure +NESTED(__start, 0, ra) + move a0, sp # Pointer to ELF entry structure move a1, v0 # Kernel-provided atexit() pointer + and sp, -16 # Align stack to 16 bytes - ld t9, %call16(__libc_init)(gp) - jalr t9 + jal __libc_init + teq zero, zero # Crash if we return END(__start)