search for: jal

> ~/Desktop/Sanjeev/LLVM/llvm-2.7/Release/lib/libLLVMgold.so --eh-frame-hdr > -melf_i386 -dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o Ok, this way you're generating code for x86 > /usr/lib/crti.o > /usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0/crtbegin.o > -L/usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0  -L/usr/local/lib -lgcc > --as-needed -lgcc_s --no-as-needed -lc -lgcc

Hello, I'm using gold linker now to see if there can be any performance gain. Also using latest gcc version (4.4.4) and latest binutils. But when I'm compiling llvm-gcc, I'm getting this error. /home/jal/llvm-gcc-4.2-2.7.source/host-i686-pc-linux-gnu/gcc/xgcc -B/home/jal/llvm-gcc-4.2-2.7.source/host-i686-pc-linux-gnu/gcc/ -B/usr/local/arm-v7a8-linux-gnueabi/bin/ -B/usr/local/arm-v7a8-linux-gnueabi/lib/ -isystem /usr/local/arm-v7a8-linux-gnueabi/include -isystem /usr/local/arm-v7a8-linux-gnueabi/sys...

Hi list-members can anybody tell me why > pairwise.t.test(val, fac) produces an empty p-table. As shown below: Pairwise comparisons using t tests with pooled SD data: val and fac AS AT Fhh Fm Fmk Fmu GBS Gf HFS Hn jAL Kol R_Fill AT - - - - - - - - - - - - - Fhh - - - - - - - - - - - - - Fm - - - - - - - - - - - - - Fmk - - - - - - - - - - - - - Fmu - - - - - - - - - - - - - GBS -...

Sorry for not explaining well. After compiling with g++-cross g++-cross -c a.c I do link using this command /gold_binutils/build/gold/ld-new -plugin ~/Desktop/Sanjeev/LLVM/llvm-2.7/Release/lib/libLLVMgold.so --eh-frame-hdr -melf_i386 -dynamic-linker /lib/ld-linux.so.2 /usr/lib/crt1.o /usr/lib/crti.o /usr/local/lib/gcc/i686-pc-linux-gnu/4.2.0/crtbegin.o

I'm trying to add support for inline assembly and I keep getting this error: <jal> "<inline asm>:1:2: error: invalid instruction" which is due to the fact that MatchInstructionImpl() returns Match_MnemonicFail. This function is tablegen'ed in XXXGenAsmMatcher.inc and for some reason it can't find JAL even though I can clearly see it in both MatchTable0...

...# %entry addiu $sp, $sp, -24 sw $ra, 20($sp) # 4-byte Folded Spill addiu $2, $sp, 56 sw $2, 16($sp) addiu $2, $2, 8 sw $2, 16($sp) lw $5, 60($sp) lw $4, 56($sp) jal _Z6reportx nop lw $2, 16($sp) #problem starts here addiu $3, $2, 4 #problem stops here sw $3, 16($sp) lw $4, 0($2) jal _Z6reporti nop lw $2, 16($sp) addiu $3, $2, 8 sw $3, 16($sp)...

...o1b: 20024: 00 00 00 00 nop 20028: 3c 19 00 02 lui $25, 2 2002c: 08 00 80 08 j 131104 <foo1a> foo2: 20030: 00 00 00 00 nop 20034: 3c 19 00 02 lui $25, 2 20038: 08 00 80 0c j 131120 <foo2> 2003c: 27 39 00 30 addiu $25, $25, 48 __start: 20040: 0c 00 80 0a jal 131112 <foo1b+0x4> 20044: 00 00 00 00 nop 20048: 0c 00 80 0d jal 131124 <foo2+0x4> 2004c: 00 00 00 00 nop 20050: 0c 00 80 0e jal 131128 <foo2+0x8> 20054: 00 00 00 00 nop 20058: 0c 00 80 0d jal 131124 <foo2+0x4> 2005c: 00 00 00 00 nop 20060: 0c...

...ra,12(sp) 6: 06300793 li a5,99 a: 842a mv s0,a0 c: 00a7cb63 blt a5,a0,22 <.L2> 10: 85aa mv a1,a0 12: 00000537 lui a0,0x0 16: 00050513 mv a0,a0 1a: 00000317 auipc t1,0x0 1e: 000300e7 jalr t1 00000022 <.L2>: 22: 40b2 lw ra,12(sp) 24: 8522 mv a0,s0 26: 4422 lw s0,8(sp) 28: 0141 addi sp,sp,16 2a: 8082 ret And after linking: 00010164 <foo>: 10164: 1141 ad...

...a mv s0,a0 >> c: 00a7cb63 blt a5,a0,22 <.L2> >> 10: 85aa mv a1,a0 >> 12: 00000537 lui a0,0x0 >> 16: 00050513 mv a0,a0 >> 1a: 00000317 auipc t1,0x0 >> 1e: 000300e7 jalr t1 >> >> 00000022 <.L2>: >> 22: 40b2 lw ra,12(sp) >> 24: 8522 mv a0,s0 >> 26: 4422 lw s0,8(sp) >> 28: 0141 addi sp,sp,16 >> 2a: 8082 ret >> >> And a...

...g253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32 %vreg247, %vreg248; AFGR64:%vreg261,%vreg247,%vreg248 4512B ADJCALLSTACKDOWN 16, %SP<imp-def>, %SP<imp-use> 4528B %D6<def> = COPY %vreg243; AFGR64:%vreg243 4544B JAL <ga:@sin>, <regmask %FP %RA %D10 %D11 %D12 %D13 %D14 %D15 %F20 %F21 %F22 %F23 %F24 %F25 %F26 %F27 %F28 %F29 %F30 %F31 %S0 %S1 %S2 %S3 %S4 %S5 %S6 %S7 >, %RA<imp-def,dead>, %D6<imp-use,kill>, %SP<imp-def>, %D0<imp-def> 4560B ADJCALLSTACKUP 16, 0, %SP<imp-def&g...

...ction Attrs: nounwind define i32 @foo() #0 { %1 = load i32, i32* getelementptr inbounds (%struct.Date, %struct.Date* @date, i32 0, i32 2), align 4 ret i32 %1 } which yields the following assembly lines ... MOVI $r0, date LD $r4, $r0, 8 // load the content of [$r0 + 8] into return register $r4 JAL ... When I look at the text section (llvm-objdump -s output), I see this 0000 00c2 This is the correct MOVI opcode but the instead of the 0s, I should see the address of 'date' The ouput of llvm-objdump -r -t is this: RELOCATION RECORDS FOR [.rel.text]: 00000000 R_XXX_MOVI date...

To reduce memory consumption clobbered registers are handled with RegisterMask machine operands which contain a bitset of all registers clobbered. - Matthias > On Jul 29, 2015, at 3:00 PM, Daniel Sanders <daniel.sanders at imgtec.com> wrote: > > I believe I've identified the problem with almabench but I haven't found the root cause in the compiler yet. > > The

...addiu $sp, $sp, -24 > sw $ra, 20($sp) # 4-byte Folded Spill > addiu $2, $sp, 56 > sw $2, 16($sp) > addiu $2, $2, 8 > sw $2, 16($sp) > lw $5, 60($sp) > lw $4, 56($sp) > jal _Z6reportx > nop > > lw $2, 16($sp) > #problem starts here > > addiu $3, $2, 4 > > #problem stops here > sw $3, 16($sp) > lw $4, 0($2) > jal _Z6reporti > nop > lw $2,...

Hi, Does lld support linker relaxation that may shrink code size? As far as I see lld seems to assume that the content of input sections to be fixed other than patching up relocations, but I believe some targets may benefit the extra optimization opportunity with relaxation. Specifically, I'm currently working on adding support for RISC-V in lld, and RISC-V heavily relies on linker relaxation

...ut is arguably more correct since we have no real stack frame. - Don't allocate extra stack space. We need none on 64-bit, and only 16 bytes on 32-bit. - Align the stack pointer in the (unlikely) event it is misaligned. - Don't load the gp register - it is useless in non-PIC code. - Use jal in 64-bit code. - Crash if __libc_start returns (teq should causes a trap exception). Signed-off-by: James Cowgill <james.cowgill at mips.com> Link: https://www.zytor.com/pipermail/klibc/2018-March/003982.html Signed-off-by: Ben Hutchings <ben at decadent.org.uk> --- usr/klibc/arch/m...

...ain(){ return function_0(8, 9); } I compile it as below llvm-gcc main.c -emit-llvm -c -O3 -o main.bc llc main.bc -relocation-model=static -march=mips -O0 -o main.s It seems no argument is provided to function_0 ... addiu $sp, $sp, -8 sw $ra, 0($sp) jal function_0 nop ... What's the reason? Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100128/56d216bc/attachment.html>

I created a DomU with a dedicated network connection script path=''/usr/lib/xen/scripts/vif-dedicated'' Having run the virtual machine I now destroy the domain, undefine it, change the script to script path=''/usr/lib/xen/scripts/vif-vnic'' define the domain and try to start it. This fails. If I change the assigned MAC address the newly defined virtual

...the transformation and match them to my LISR & CALL instructions in my XXXInstrInfo.td TableGen file. I've been looking at how the Mips target has hi/lo relocations to handle 16-bits of an address at a time, but I don't see how the relocations are inserted(?) into the patterns for the JAL/JALR nodes. Does anyone have any advice on the best way to do this, and/or how the Mips addresses are handled? 2) I'm also not sure how (or at what stage of codegen) to check if the callee lives in the same instruction segment. How can I compare a call instruction's address with that of...

...elp implementing relocations Hi Josh, On Wed, 13 Mar 2019 at 00:18, Josh Sharp via llvm-dev <llvm-dev at lists.llvm.org> wrote: > which yields the following assembly lines > > ... > MOVI $r0, date > LD $r4, $r0, 8 // load the content of [$r0 + 8] into return register $r4 > JAL > ... > > When I look at the text section (llvm-objdump -s output), I see this > > 0000 00c2 > > This is the correct MOVI opcode but the instead of the 0s, I should see the address of 'date' I don't think you should see "date" there yet. That's the wh...

Hi, I noticed that klibc started crashing on 64-bit MIPS and in my quest to fix the bug I got a bit carried away and fixed a few other things as well. Here are various miscellaneous MIPS patches, although the first patch is the important one. Thanks, James *** BLURB HERE *** James Cowgill (5): mips64: compile with -mno-abicalls mips: use -Ttext-segment when linking shared library