search for: isimm

..., 2012 at 9:24 AM, Kai <kai at redstar.de> wrote: > Hi! > > I added 2 more tests and also refined an assert statement. Applies cleanly > to r148473 now. Are there more comments on the code? Thank you!! + assert(Inst.getOperand(0).isReg() && + (Inst.getOperand(ImmOp).isImm() || + (Inst.getOperand(ImmOp).isExpr() && + Inst.getOperand(ImmOp).getExpr()->getKind() == MCExpr::SymbolRef) && + static_cast<const MCSymbolRefExpr*>(Inst.getOperand(ImmOp).getExpr())->getKind() == MCSymbolRefExpr::VK_SECREL) && Just asserting "In...

Hi! I added 2 more tests and also refined an assert statement. Applies cleanly to r148473 now. Are there more comments on the code? Thank you!! Regards Kai On 01.01.2012 22:01, Eli Friedman wrote: > On Sun, Jan 1, 2012 at 10:44 AM, Kai<kai at redstar.de> wrote: >> Happy new year to all! >> >> The attached patch adds TLS support for x86_64-pc-win32 and x86-pc-win32.

...ef MFENCE : I<0xAE, MRM6m, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< [HasSSE2]>; In X86CodeEmitter.cpp in emitInstruction case X86II::MRM6m: case X86II::MRM7m: { intptr_t PCAdj = (CurOp+4 != NumOps) ? (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm (Desc) : 4) : 0; ... If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so we to get the 4th operand from the MFENCE operation which has no operands so we get an error. I'm not sure what this code is trying to do. Should the condition...

Hello all, currently the SPU backend does not handle big stack frames (>16*511 bytes) nicely. llc asserts on malformed machine instructions. (Assertion `MI->getOperand(OpNo).isImm() && "printDFormAddr first operand is not immediate") E.g. the function: define i32 @foo() nounwind { entry: %retval = alloca i32 %big_data = alloca [1000 x i32] store i32 3840, i32* %retval, align 4 br label %return return: %retval2 = load i32* %retval r...

...p;& + "invalid scale for 16-bit memory reference"); + + if (IndexReg16 & 2) + RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); + else + RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); + } + + if (Disp.isImm() && isDisp8(Disp.getImm())) { + // Use [REG]+disp8 form if we can, and for [BP] which cannot be encoded. + if (BaseRegNo == N86::EBP || Disp.getImm() != 0) { + EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS); + EmitImmediate(Disp, MI.getLoc(), 1...

...BB(trgBlock); these are working fine. When creating an compare instruction like cmp r0, 1 with:      BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1); I get the following error:     .../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not an immediate"' failed. Which even after hours I can't make sense why the operand kind is wrong. Another thing I noticed is that using ARM::tB results in the following error: .../include/llvm/ADT/SmallVector.h:154: const T& llvm::SmallV...

...ts), (ins), > "mfence", [(int_x86_sse2_mfence)]>, TB, Requires< > [HasSSE2]>; > > In X86CodeEmitter.cpp in emitInstruction > > case X86II::MRM6m: case X86II::MRM7m: { > intptr_t PCAdj = (CurOp+4 != NumOps) ? > (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm > (Desc) : 4) : 0; > ... > > If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so > we to get the 4th operand from the MFENCE operation which has no > operands so we get an error. I'm not sure what this code is trying to >...

..."mfence", [(int_x86_sse2_mfence)]>, TB, Requires< >> [HasSSE2]>; >> >> In X86CodeEmitter.cpp in emitInstruction >> >> case X86II::MRM6m: case X86II::MRM7m: { >> intptr_t PCAdj = (CurOp+4 != NumOps) ? >> (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm >> (Desc) : 4) : 0; >> ... >> >> If I'm reading the code correctly, the NumOps is 0 and CurOp is 0 so >> we to get the 4th operand from the MFENCE operation which has no >> operands so we get an error. I'm not sure what this...

On Feb 22, 2010, at 6:08 AM, Kalle.Raiskila at nokia.com wrote: > Hello all, > > currently the SPU backend does not handle big stack frames (>16*511 > bytes) nicely. llc asserts on malformed machine instructions. > (Assertion `MI->getOperand(OpNo).isImm() && "printDFormAddr first > operand is not immediate") Sounds fine to me in general. Please write a testcase for this though. Also, this patch causes the CodeGen/CellSPU/call.ll regression test to fail. Please investigate and send an updated patch (with a testcase), thanks...

...inter.cpp void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { O << '%' << getRegisterName(Op.getReg()); } else if (Op.isImm()) { ... } else { assert(Op.isExpr() && "unknown operand kind in printOperand"); // HERE I remove the '$' to make it work O << '$' << *Op.getExpr(); } I hope someone is good in this thing! Thank you for your help, Patrick Marlier...

...case X86::BT64ri8: case X86::BT32ri8: case X86::BT16ri8: { assert(OldMI->getNumOperands() >= 2); MachineOperand &Reg = OldMI->getOperand(0); MachineOperand &Imm = OldMI->getOperand(1); assert(Reg.isReg()); assert(Imm.isImm()); imm = Imm.getImm(); if (imm >= 32) continue; kill = getKillRegState(Reg.isKill()); switch (Reg.getReg()) { default: assert(false); case X86::RAX: case X86::EAX: case X86::AX:...

Dear all, I have written an assembler which reads assembly instructions and produces the equivalent binary. I have a problem. Although I set the bit range and immediate type for an instruction like add which accepts a register and an immediate value, I can simply overflow that value and llvm/tablegen doesn't care! for example for a i8imm imm value (bits<8> val) these two produce the

...ale for 16-bit memory reference"); > + > + if (IndexReg16 & 2) > + RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); > + else > + RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); > + } > + > + if (Disp.isImm() && isDisp8(Disp.getImm())) { > + // Use [REG]+disp8 form if we can, and for [BP] which cannot be > encoded. > + if (BaseRegNo == N86::EBP || Disp.getImm() != 0) { > + EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS); > + EmitImmed...

...ing fine. > When creating an compare instruction like cmp r0, 1 with: > > BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1); > > I get the following error: > > .../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not an immediate"' failed. > According to ARMInstrThumb.td, tCMPi8's source arguments are reg, imm and there is no explicit destination register, so what you want is: BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8)).addReg(ARM::R0).addImm(1); -Tom...

Chris Lattner skrev: > On Feb 22, 2010, at 6:08 AM, Kalle.Raiskila at nokia.com wrote: >> currently the SPU backend does not handle big stack frames (>16*511 >> bytes) nicely. llc asserts on malformed machine instructions. >> (Assertion `MI->getOperand(OpNo).isImm() && "printDFormAddr first >> operand is not immediate") > > Sounds fine to me in general. Please write a testcase for this > though. Attached. > Also, this patch causes the CodeGen/CellSPU/call.ll > regression test to fail. Oops. Sorry about that. I...

On 06/21/2010 08:21 PM, Eric Christopher wrote: > On Jun 21, 2010, at 2:56 AM, Patrick Marlier wrote: > > >> Hello, >> >> This bug affects all LLVM versions from 2.6 to trunk : >> http://llvm.org/bugs/show_bug.cgi?id=5081 >> >> The workaround I found is to add this : >> >> Index: lib/Target/X86/X86Instr64bit.td >>

...rgetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups) const { const MCOperand &MO = MI.getOperand(OpNo); if (MO.isReg()) { unsigned Reg = MO.getReg(); unsigned RegNo = getMipsRegisterNumbering(Reg); return RegNo; } else if (MO.isImm()) { return static_cast<unsigned>(MO.getImm()); } else if (MO.isFPImm()) { return static_cast<unsigned>(APFloat(MO.getFPImm()) .bitcastToAPInt().getHiBits(32).getLimitedValue()); } else if (MO.isExpr()) { const MCExpr *p_expr = MO.getExpr(); Fixups.pus...

On Fri, 2015-02-20 at 13:47 -0500, Rafael Espíndola wrote: > > Your task, should you choose to accept it, is to make it cope with other > > forms of relaxation where necessary. > > And if not, please open a bug :-) http://llvm.org/bugs/show_bug.cgi?id=22662 FWIW I could reproduce the 'movl foo, %ebx' one but a relative jump *was* using 16 bits (although gas uses 8):

...X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, > raw_ostream &O) { > const MCOperand &Op = MI->getOperand(OpNo); > if (Op.isReg()) { > O << '%' << getRegisterName(Op.getReg()); > } else if (Op.isImm()) { > ... > } else { > assert(Op.isExpr() && "unknown operand kind in printOperand"); > // HERE I remove the '$' to make it work > O << '$' << *Op.getExpr(); > } > Hrm. Something is wonky here. Can you file a testcas...

...ating an compare instruction like cmp r0, 1 with: >> >> BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8),0).addImm(1); >> >> I get the following error: >> >> .../include/llvm/MC/MCInst.h:81: int64_t llvm::MCOperand::getImm() const: Assertion `isImm() && "This is not an immediate"' failed. >> > According to ARMInstrThumb.td, tCMPi8's source arguments are reg, imm and > there is no explicit destination register, so what you want is: > > BuildMI(BB, BB.end(), DL, TII->get(ARM::tCMPi8)).addReg(ARM::R...