search for: iscommutative

Displaying 20 results from an estimated 49 matches for "iscommutative".

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2009 Dec 07
2
[LLVMdev] How to use property 'isCommutable' in target description file?
Hi everyone, I practice writing target description file with MSP430 reference. I add a multiply-and-add instruction as below: let isTwoAddress=1 in { def MULADD:Pseudo<(out GR16:$dst), (ins GR16:$src1, GR16:$src2, GR16:$src3), "muladd\t{$dst, $src2, $src3}", [(set GR16:$dst, (add GR16:$src1, (mul GR16:$src2,
2009 Dec 07
0
[LLVMdev] How to use property 'isCommutable' in target description file?
Hello > How can i tell the system X=A*B + C == X = B*A + C == X=C+A*B == X=C+B*A by > property 'isCommutable'? Is it necessary to do that? Most probably you will need to write a special hook to commute this instruction. However, everything depends on your target (e.g. if there is an output register tied to one of the input). > *** Another question: Why set isCommutable = 1 in
2009 Dec 08
1
[LLVMdev] How to use property 'isCommutable' in target description file?
Thanks to Anton. Frankly said i don't know the exact meaning and purpose of 'isCommutable'. By my opinion "add.w r6, r7" != "add.w r7, r6", so we shouldn't set isCommutable = 1. Who would like give an example to demonstrate what benifit it has if 'isCommuatble=1' in instruction selection, register allocation or other process? Regards 2009/12/7,
2012 Jul 05
2
[LLVMdev] bug in tablegen?
I think that what I did originally should have worked and the bug was correct as I reported it. Here is an alternate implementation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList,
2012 Jul 05
0
[LLVMdev] bug in tablegen?
This variant works: class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx,
2014 Apr 22
2
[LLVMdev] where is F7 opcode for TEST instruction on X86?
hi, at the moment, TEST instruction is defined with 0xf7 opcode, as demonstrated below. $ echo "0xf7 0xc0 0x00 0x00 0x00 0x22"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86 .section __TEXT,__text,regular,pure_instructions testl $570425344, %eax ## imm = 0x22000000 however, i cannot find anywhere this F7 opcode is defined in
2009 Apr 16
3
[LLVMdev] Help me improve two-address code
Evan Cheng wrote: > On Apr 16, 2009, at 3:17 PM, Greg McGary wrote: > >> Is there some optimizer knob I'm not turning properly? In more complex >> cases, GCC does poorly with two-address operand choices and so bloats >> the code with unnecessary register moves. I have high hopes LLVM >> can do better, so this result for a simple case is bothersome. >>
2012 Jul 03
3
[LLVMdev] bug in tablegen?
Not sure what you mean. I.OutOperandList == (outs CPU16Regs:$rx) I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) On 07/02/2012 09:26 PM, Sean Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args though... which makes me wonder what is
2012 Jul 04
0
[LLVMdev] bug in tablegen?
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : // ... This class has template args. You don't specify them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote: > Not sure what you mean.
2012 Jul 03
2
[LLVMdev] bug in tablegen?
I've filed the following bug. Maybe I'm doing something stupid here or maybe someone knows of a workaround. The following fragment from mips16 (not yet checked into main source). The problem is that I should be able to pass parameters: I.OutOperandList, I.InOperandList But instead, I must back substitute what I know the values of these are. (outs CPU16Regs:$rx), (ins CPU16Regs:$ry,
2018 Nov 07
2
how to add a instruction
Hi,every one. I' in trouble again. I want add a new intrinsic mapping a new instruction. I add the int_x86_max_qb as fllowing: def int_x86_max_qb: GCCBuiltin<"__builtin_x86_max_qb">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [Commutative]>; BUILTIN(__builtin_x86_max_qb, "iii", "") I define the intrinsic as Pseudo instruction,it
2009 Apr 17
0
[LLVMdev] Help me improve two-address code
On Apr 16, 2009, at 4:25 PM, Greg McGary wrote: > Evan Cheng wrote: >> On Apr 16, 2009, at 3:17 PM, Greg McGary wrote: >> >>> Is there some optimizer knob I'm not turning properly? In more >>> complex >>> cases, GCC does poorly with two-address operand choices and so >>> bloats >>> the code with unnecessary register moves. I
2012 Jul 03
0
[LLVMdev] bug in tablegen?
I think you're missing the template args for `FRRR16_ins` in the first argument. The switch in TGParser::ParseType() doesn't cover the case of types with template args though... which makes me wonder what is going on inside of TableGen to make `I.f` and `I.AsmString` valid... --Sean Silva On Mon, Jul 2, 2012 at 8:07 PM, reed kotler <rkotler at mips.com> wrote: > I've filed
2010 Sep 09
0
[LLVMdev] Possible missed optimization? 2.0
On Sep 9, 2010, at 12:59 PM, Borja Ferrer wrote: > Hello, i've noticed a new possible missed optimization while testing more trivial code. > This time it's not a with a xor but with a multiplication instruction and the example is little bit more involved. > > C code: > > typedef short t; > t foo(t a, t b) > { > t a4 = a*b; > return a4; > } >
2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Tue, Feb 10, 2009 at 8:27 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Bill, > Sorry if I wasn't clear enough. I wasn't referring to multiclass's that > define other classes, but with using patterns inside of a multiclass to > reduce redundant code. > For example: > multiclass IntSubtract<SDNode node> > { > def _i8 : Pat<(sub
2012 Sep 16
1
[LLVMdev] Pattern class
Here is a simple place I wanted to use it. ... On multiply, the result implicit is placed in a 64 bit hi/lo register. // // Format: MFLO rx MIPS16e // Purpose: Move From LO Register // To copy the special purpose LO register to a GPR. // def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { let Uses = [LO]; let neverHasSideEffects = 1; } // // Pseudo Instruction for mult //
2013 Mar 20
2
[LLVMdev] Strange spill behaviour
Hi, While working some more on the backend, I've added callee register saving and have come across something odd (I assume its because i've not implemented something), this is with optimisations which makes it even more odd : MOV.L [R7+ 12], R1 ; 4-byte Folded Spill MOV.L [R7+ 8], R2 ; 4-byte Folded Spill ADD.L R0,R0 + R1 ADD.L
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Bill, Sorry if I wasn't clear enough. I wasn't referring to multiclass's that define other classes, but with using patterns inside of a multiclass to reduce redundant code. For example: multiclass IntSubtract<SDNode node> { def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; def _i32 : Pat<(sub
2009 Jul 06
2
[LLVMdev] Help on DAG pattern matching string
Hi Bill, Yes, there are other patterns. I tried commenting out all the other instructions definitions and I still get this error. After debugging TblGen I found that the second pattern is being generated as a variant of the first. I think the reason is that the PADD instruction is inheriting the commutative property from ADD defined inTargetSelectionDAG.td. The variant ends up being the same
2010 Sep 04
6
[LLVMdev] Possible missed optimization?
Hello, while testing trivial functions in my backend i noticed a suboptimal way of assigning regs that had the following pattern, consider the following function: typedef unsigned short t; t foo(t a, t b) { t a4 = b^a^18; return a4; } Argument "a" is passed in R15:R14 and argument "b" is passed in R13:R12, the return value is stored in R15:R14. Producing the