search for: iscommut

...1, GR16:$src2, GR16:$src3), "muladd\t{$dst, $src2, $src3}", [(set GR16:$dst, (add GR16:$src1, (mul GR16:$src2, GR16:$src3)))]> } How can i tell the system X=A*B + C == X = B*A + C == X=C+A*B == X=C+B*A by property 'isCommutable'? Is it necessary to do that? *** Another question: Why set isCommutable = 1 in ADD16rr but NOT set in ADD16ri? let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "add.w\t{$src2, $ds...

Hello > How can i tell the system X=A*B + C == X = B*A + C == X=C+A*B == X=C+B*A by > property 'isCommutable'? Is it necessary to do that? Most probably you will need to write a special hook to commute this instruction. However, everything depends on your target (e.g. if there is an output register tied to one of the input). > *** Another question: Why set isCommutable = 1 in ADD16rr but NOT...

Thanks to Anton. Frankly said i don't know the exact meaning and purpose of 'isCommutable'. By my opinion "add.w r6, r7" != "add.w r7, r6", so we shouldn't set isCommutable = 1. Who would like give an example to demonstrate what benifit it has if 'isCommuatble=1' in instruction selection, register allocation or other process? Regards 2009/12/...

...gt;(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; I think that the problem has to do with the operaand lists not working if there is substitution required. Tablegen is only complaining about $rx, $ry and $rz . On 07/03/2012 05:35...

...$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } On 07/05/2012 03:11 PM, reed kotler wrote: > I think that what I did originally should have worked and the bug was > correct as I reported it. > > Here is an alternate implementation which has the same problem. > > class ArithLogicRT...

...$570425344, %eax ## imm = 0x22000000 however, i cannot find anywhere this F7 opcode is defined in lib/Target/X86/X86InstrArithmetic.td. we only have TEST defined with F6 & other opcode like below. any hint please? thanks. let isCompare = 1 in { let Defs = [EFLAGS] in { let isCommutable = 1 in { def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>; def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>; def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>; def TES...

Evan Cheng wrote: > On Apr 16, 2009, at 3:17 PM, Greg McGary wrote: > >> Is there some optimizer knob I'm not turning properly? In more complex >> cases, GCC does poorly with two-address operand choices and so bloats >> the code with unnecessary register moves. I have high hopes LLVM >> can do better, so this result for a simple case is bothersome. >>

...f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), >> // tablegen bug: should be I.OutOperandList, I.InOperandList, >> I.AsmString, >> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], >> I.Itinerary> { >> let isCommutable = isComm; >> let isReMaterializable = 1; >> } >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...16Regs:$ry, CPU16Regs:$rz), >>> // tablegen bug: should be I.OutOperandList, >>> I.InOperandList, >>> I.AsmString, >>> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], >>> I.Itinerary> { >>> let isCommutable = isComm; >>> let isReMaterializable = 1; >>> } >>> _______________________________________________ >>> LLVM Developers mailing list >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo...

...Node OpNode, bit isComm = 0>: FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // tablegen bug: should be I.OutOperandList, I.InOperandList, I.AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], I.Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; }

...ndled immediate encoding " But when I write the same as the instruction IMUL32rr, there is no error in compiling.(I don't use the EFLAGS at all, so I think it's wrong. Indeed, it made a error when using it.) let Defs = [EFLAGS] in { let Constraints = "$src1 = $dst" in { let isCommutable = 1 in { def max_qb : I<0xF0,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2}", [(set GR32:$dst,(X86max_qb GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul16Reg]>,OpSize32 ; } } What I don't understand is that how I define "let...

...; ISD::ADD node is commutative. But it doesn't mean the target specific instruction it is selected to has to be commutative. > > ... and assumed it was sufficient, since I saw no other targets making > special arrangements. In X86InstrInfo.td, ADD32rr (and lots others) are marked isCommutable. Evan > > I see no obvious (to me, anyway 8^) "copy instruction" property. The > insn in question is generated by copyRegToReg(), and satisfies the > isMoveInstr() predicate. > > G > > _______________________________________________ > LLVM Developers mail...

...t;: > FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), > // tablegen bug: should be I.OutOperandList, I.InOperandList, > I.AsmString, > [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], > I.Itinerary > { > let isCommutable = isComm; > let isReMaterializable = 1; > } > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...nt "a" is passed in R15:R14, argument "b" in R13:R12, the return value is stored in R15:R14. > The mul instruction takes in two 8bit regs and returns a 16bit result in R1:R0, this is handled in the selectionDAG same way as x86 (btw mul is marked as commutable). Note that the isCommutable flag is only really useful for two-address instructions. If the two inputs are not constrained, nothing is really won by swapping them. [...] > The difference between both versions is that the second has one instruction less and saves a scratch register. > If we start by multiplying th...

...mmutable = 0> { // Scalar operation, reg+reg. def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> { let isCommutable = Commutable; } // Scalar operation, reg+mem. def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2), !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (OpNode...

...e From LO Register // To copy the special purpose LO register to a GPR. // def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { let Uses = [LO]; let neverHasSideEffects = 1; } // // Pseudo Instruction for mult // def MultRxRy16: FMULT16_ins<"mult", IIAlu> { let isCommutable = 1; let neverHasSideEffects = 1; let Defs = [HI, LO]; } def: Mips16Pattern<(mul CPU16Regs:$l, CPU16Regs:$r), [(MultRxRyRz16 CPU16Regs:$l, CPU16Regs:$r), (Mflo16) ]>; Without the list of instructions feature in the Pattern class, I am forced to make a pseudo that has b...

...on't make use of R1 or R2, Calling convention states R0-R3 are used as inputs to a function. R1-R4 are marked as calleesaved. From the above code I cannot see any reason why R1 & R2 are being spilled, I assume the fault lies in my tablegen definitions (relevant ones reproduced below) : let isCommutable=1 in { def ADD32rrr : M819Inst<(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),"ADD.L\t{$dst,$src1 + $src2}",[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; } def ADD32rri : M819Inst<(outs GR32:$dst),(ins GR32:$src1, i32imm:$src2),"ADD.L\t{$dst,$src1 + $src2}",[(set...

Bill, Sorry if I wasn't clear enough. I wasn't referring to multiclass's that define other classes, but with using patterns inside of a multiclass to reduce redundant code. For example: multiclass IntSubtract<SDNode node> { def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; def _i32 : Pat<(sub

...e reason is that the PADD instruction is inheriting the commutative property from ADD defined inTargetSelectionDAG.td. The variant ends up being the same as the original causing the error later on. If all this is correct then how can I mark the node to be non-commutable? I tried using "let isCommutable = 0" in the instruction definition but didn't seem to work. Thanks, Javier On 7/4/2009 3:08 PM, Bill Wendling wrote: > Are there any other patterns in your TD file? If so, then one of the > ones before this pattern will match everything, and this pattern will > never be ma...

Hello, while testing trivial functions in my backend i noticed a suboptimal way of assigning regs that had the following pattern, consider the following function: typedef unsigned short t; t foo(t a, t b) { t a4 = b^a^18; return a4; } Argument "a" is passed in R15:R14 and argument "b" is passed in R13:R12, the return value is stored in R15:R14. Producing the