search for: instrw

...in this same file, I find the lines presented below, which are mapping the SchedReadWrite to, for example, the ANDri instruction. // ===---------------------------------------------------------------------===// // Subtarget-specific overrides. Map opcodes to list of SchedReadWrite types. // def : InstRW< [WriteALU], (instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr", "BICrr")>; This same instruction is defined in the ARMInstrInfo.td as inheriting from AsI1_bin_irs (s...

...of `AArch64SchedA57.td`, as shown below ``` def A57WriteFPVMAD : SchedWriteRes<[A57UnitV]> { let Latency = 9; } def A57WriteFPVMAQ : SchedWriteRes<[A57UnitV, A57UnitV]> { let Latency = 10; } def A57ReadFPVMA5 : SchedReadAdvance<5, [A57WriteFPVMAD, A57WriteFPVMAQ]>; def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>; def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA5], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>; ``` In this code, an 128bit ASIMD FP multiply accumulate(FMLA/FMLS Q-form) requires...

I'm sure the x86 scheduler models are causing bloat. Every time a single instruction appears on a line by itself like this in a scheduler model: def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>; It causes that instruction to be its own group in the generated output. And its replicated for each CPU. We should look into better using regular expressions or taking advantage of the fact that InstRW can take a list of instructions. Th...

[I tweaked the subject, #262824 did not introduce the problem, it is just the version I am first seeing this problem] A quick update - I have added 'Sched<[]>' as a base class for all instructions, and also: let hasNoSchedulingInfo = 1; to all the Pseudos, but while most of the errors have gone, I still get the diagnostic for 'COPY' thus: error : No schedule

> On Mar 17, 2018, at 4:04 PM, Craig Topper via cfe-dev <cfe-dev at lists.llvm.org> wrote: > > I'm sure the x86 scheduler models are causing bloat. Every time a single instruction appears on a line by itself like this in a scheduler model: > > def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>; > > It causes that instruction to be its own group in the generated output. And its replicated for each CPU. We should look into better using regular expressions or taking advantage of the fact that InstRW can take a list of instru...

...te: > > > On Mar 17, 2018, at 4:04 PM, Craig Topper via cfe-dev < > cfe-dev at lists.llvm.org> wrote: > > I'm sure the x86 scheduler models are causing bloat. Every time a single > instruction appears on a line by itself like this in a scheduler model: > > def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>; > > It causes that instruction to be its own group in the generated output. > And its replicated for each CPU. We should look into better using regular > expressions or taking advantage of the fact that InstRW can take a list...

Hi list, Is it possible to simulate load to store forwarding on aarch64 with MI scheduling model on AArch64? For instance $x0 data latency in the example below should be 1 cycle ldr $x0, [$x1] str $x0, [$x2] But it should be 4 cycles if we have another instruction: ldr $x0, [$x1] add $x0, $x0, 4 For ALU instructions it’s possible to use either ReadAdvance or SchedReadAdvance, but I don’t see

.... Then you would need to change the ReadAdr line in your subtarget to an override: def : ReadAdvance<ReadAdr, 3, [WriteLD]> Or instead you can just add a rule in your subtarget listing the opcodes or using a regex, and using the ReadAdr resource that you defined in the same file. def : InstRW<[WriteST, ReadAdr], (instregex "ST(someregex)$")>; Being careful about store-pair and vector stores. Then you always want to debug your target’s llvm-tblgen command by adding a flag -debug-only=subtarget-emitter And even trace the schedule for some simple cases with -debug-only=m...

Thanks for raising this. This is something we've recently been looking at too at Sony, as over the course of PS4's lifetime so far we've seen our clang executable on Windows approximately double in size, which isn't ideal for things like distributed build systems. A graph of clang.exe size on our internal staging branch matches yours closely with it being more of a death by a

Hi all, I recently did a run where I built clang executables on FreeBSD 12-CURRENT [1], from trunk r250000 (2015-10-11) all through r327700 (2018-03-16), with increments of 100 revisions. This is mainly meant as an archive, for easily doing bisections, but there are also some interesting statistics. From r250000 through r327700: * the total (stripped) executable size grew by approximately 43% *

Hi all, I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: name LDADDALX; class 872 microops 65535 I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong? Cheers, Tom #define GET_REGINFO_ENUM

...> */ I bet the problem is that “WriteAtomic” is marked unsupported, so it gets an invalid sched class. The invalid NumMicroOps means that the scheduler will assert if it ever sees that instruction. def : WriteRes<WriteAtomic, []> { let Unsupported = 1; let NumMicroOps = 2; } def : InstRW<[THX2T99Write_16Cyc_I012, WriteAtomic], (instrs LDADDALB, LDADDALH, LDADDALW, LDADDALX)>; To debug things like this, look in AArch64GenSubtargetInfo.inc. Or use the schedcover.py script. -Andy

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

...kwards, normally dispatch determines the available subset of pipelines). That might not be a significant issue as far as the scheduler output is concerned but it seemed strange to me and it makes me doubt that I've fully understood it. One thing about the attached WIP. I'm using ItinRW and InstRW at the moment but I'm planning on migrating the ItinRW's to InstRW. The reason I'm not using the Sched<> class on each instruction is that I'm not confident that there is a common set of SchedReadWrite def's that would make sense on the full range of MIPS processor impleme...