search for: instructionset

Displaying 5 results from an estimated 5 matches for "instructionset".

2010 Oct 13
4
[LLVMdev] How to register a new LLVM backend
...ackend were: - At RiscoTargetMachine.cpp: extern "C" void LLVMInitializeRiscoTarget() { // Register the target. RegisterTargetMachine<RiscoTargetMachine> X(TheRiscoTarget); RegisterAsmInfo<RiscoMCAsmInfo> A(TheRiscoTarget); } - At Risco.td: def Risco : Target { let InstructionSet = RiscoInstrInfo; } - At RiscoTargetInfo.cpp: Target llvm::TheRiscoTarget; extern "C" void LLVMInitializeRiscoTargetInfo() { RegisterTarget<> X(TheRiscoTarget, "risco", "Risco"); } What I found suspicious was that in the last file (RiscoTargetInfo.cpp), t...
2013 Jan 31
2
[LLVMdev] Tablegen problem populating TSFlags
...d work with Tablegen, but it generates the error: "error:Invalid TSFlags bit in ADD" Here's the code: =================================== include "llvm/Target/Target.td" def MyInstrInfo : InstrInfo; def MyTarget : Target { // Information about the instructions... let InstructionSet = MyInstrInfo; } def r1 : Register<"r1"> { let Namespace = "Test"; } def RC1 : RegisterClass<"Test", [i8], 8, (add r1)>; class BitField<bits<2> x> { bits<2> Val = x; } def VALUE_0 : BitField<0>; def VALUE_1 : BitField<1>;...
2011 Jul 03
0
[LLVMdev] DLX backend
...------------===// include "DLXInstrInfo.td" def DLXInstrInfo : InstrInfo {} //===----------------------------------------------------------------------===// // Target Declaration //===----------------------------------------------------------------------===// def DLX : Target { let InstructionSet = DLXInstrInfo; } ** DLXRegisterInfo.td ********************************************************* //===- DLX.td - DLX Register definition ---*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Sour...
2012 Oct 12
3
[LLVMdev] Newbie question for registering new target with LLVM
...StringRef CPU, StringRef FS, Reloc::Model RM, CodeModel::Model CM) : LLVMTargetMachine(T, TT, CPU, FS, RM, CM) { } 8) lib/Target/Rx/Rx.td include "llvm/Target/Target.td" def RxInstrInfo : InstrInfo; def Rx : Target { let InstructionSet = RxInstrInfo; } 9) lib/Target/Rx/RxAsmPrinter.cpp using namespace llvm; extern "C" void LLVMInitializeRxAsmPrinter() { RegisterAsmPrinter<RxAsmPrinter> X(TheRxTarget); } RxAsmPrinter::RxAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) : A...
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...string AsmParserClassName = "AsmParser"; > + int Variant = 0; > + > + string CommentDelimiter = ";"; > + > + string RegisterPrefix = "r"; > + > +} > + > + > +def AMDIL : Target { > + // Pull in Instruction Info: > + let InstructionSet = AMDILInstrInfo; > + let AssemblyWriters = [AMDILAsmWriter]; > + let AssemblyParsers = [AMDILAsmParser]; > +} > > Added: llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp?rev=1...