Displaying 17 results from an estimated 17 matches for "instr_asm".
2016 May 04
4
Conditional tablegen expressions with math ops?
...dd r1, r1, r2 # r1 <- r1 + r2
There are four banks and the formula to figure out which bank a register is
in is just: r%4
Which brings me to tablegen:
We've got this in our specialized ArchInstrInfo.td:
// r1 = r2 op r3
//
class ArithOp_RR< bits<7> op,
string instr_asm,
SDNode opNode,
OperandInfo info,
InstrItinClass itin >
: FR3< op,
(outs info.regClass:$r1),
(ins info.regClass:$r2, info.regClass:$r3),
instr_asm # "\t\t$r1, $r2, $r3, " # info.sizeStr,
[(set in...
2012 Jan 19
0
[LLVMdev] Problem generating <target>GenAsmMatcher.inc
...[SDTCisInt<0>,
SDTCisSameAs<0, 1>]>;
def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
[SDNPOutGlue]>;
class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
RegisterClass RC, list<Register> DefRegs>:
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$$zero, $rs, $rt"),
[(op RC:$rs, RC:$rt)], itin> {
let rd = 0;
let shamt = 0;
let Defs = DefRegs;
}
Note:,the...
2014 Jun 10
2
[LLVMdev] Regarding Instruction definition in LLVM backend
...I have defined the registers: MYREG1_NAME and
MYREG2_NAME
in TARGETInstrInfo.td file I have the following definitions:
def simm16 : Operand<i16> {
let DecoderMethod= "DecodeSimm16";
let OperandType = "OPERAND_IMMEDIATE";
}
class SII<bits<6> op, string instr_asm, Operand Imm> :
FI<op, (outs), (ins Imm:$val), !strconcat(instr_asm,
"\t$val"), [], IIAlu> {
let rs = 0;
let rt = 0;
}
def MOV : SII<0x21, "mov", simm16>;
def : TARGETPat<(int_my_builtin_function_name (imm:$val)), (MOV imm:$val)>;...
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
...ype = llvm::DefInit*]: Assertion
`isa<X>(Val) && "cast<Ty>() argument of incompatible type!"' failed.
Looks like the incompatible types are DefInit and Init. The offending line
is in this definition:
class LoadOpIdx< bits<7> op,
string instr_asm,
OperandInfo info,
InstrItinClass itin=II_LOAD1_RR >
//
// load: r1 = mem[r2 + (r3 << sizeof(operand) ]
//
: FR3< op,
(outs info.regClass:$r1),
(ins ADDR_SHLI:$addr), //<<-this line causes assert
instr_...
2016 Oct 24
2
Instruction selection confusion at register - chooses vector register instead of scalar one
...the style of Mips MSA - see
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look
for "def ST_D", etc.
Note however that my vector unit has a separate memory space. This is why I defined
the vector store like:
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$w...
2014 Aug 05
2
[LLVMdev] Concerning not relevant argument count in TableGen Patterns.
...te a move instruction which should use two register type
operands: "/mov R1, R2/"
For this purpose I assume that the instruction definition in the
TargetInstrInfo.td file should be like:
at first I am defining the class form my instruction:
*class Mymov<bits<6> op, string instr_asm>: FI<op, (outs Regs1:$rs),
(ins Regs2:$rt),
!strconcat(instr_asm, "\t$rt, $rs"),
[], NoItinerary> {
let imm16 = 0;
}*
where *Regs1* and *Regs2* are corresponding *RegisterClasses*.
Then I need to define the instruction:
*def MOVInstr : Mymov<0x2, &qu...
2016 Oct 25
0
Instruction selection confusion at register - chooses vector register instead of scalar one
...in the style of Mips MSA - see
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look
for "def ST_D", etc.
Note however that my vector unit has a separate memory space. This is why I defined
the vector store like:
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$w...
2016 Mar 18
2
Immediate operand for load instruction, in back end
...that takes an immediate address operand. (I got inspired from Mips' MSA SIMD
extensions.)
Could you please tell me what's the right way to do it?
Here, the load class has $addrsrc which is a relative address with base a certain
register and offset:
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = mem_msa,
ComplexPattern Addr = addrimm10,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins MemOpnd:$addrsrc);
string AsmString = !s...
2012 Jan 26
2
[LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content
...MipsInstrInfo.td:833:14: error: Instruction 'LWL' has no tokens
defm LWL : LoadUnAlign32<0x22>;
How does it get a token?
Commenting out this code I got farther and found that a register that didn't have a formal def in MipsRegisterInfo.td would get flagged.
!strconcat(instr_asm, "\t$$zero, $rs, $rt"),
% tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.td
Included from Mips.td:24:
Included from MipsInstrInfo.td:1120:
Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'
def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv&qu...
2012 Sep 14
0
[LLVMdev] Seperating registers in target description string replacement without adding whitespace?
Here's an example piece of code to show you what I'm trying to do (on llvm
3.1):
class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat("+$rd=$rs ",!strconcat(instr_asm, " $rt")),
[(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
let shamt =...
2016 Dec 11
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...DwarfRegNum<[!add(RegId, 10)]>;
def VK128: RegisterClass<"Connex", [v128i1], 32, (sequence "Mask%u", 0, 31)>;
def VK128Opnd : RegisterOperand<VK128> {
let ParserMatchClass = MSA128AsmOperand;
}
class LD_INDIRECT_DESC_BASE2<string instr_asm,
ValueType TyNode,
RegisterOperand ROWD,
RegisterOperand ROWSI = ROWD,
RegisterOperand ROWSP = ROWD, // passthru register
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (out...
2016 Dec 12
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...let MIOperandInfo = (ops i8imm, RC, i32imm);
}
def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">;
def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
class LD_INDIRECT_DESC_BASE2<string instr_asm,
RegisterOperand ROWD,
RegisterOperand ROWSP = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd, VK128Opnd:$wdm);
dag InOperandList =...
2012 Feb 03
0
[LLVMdev] HELP - tblgen -gen-asm-matcher restrictions on .td content
...variant in the multi class expansion that doesn't have a string associated with it that can be used to derive the syntax.
> Commenting out this code I got farther and found that a register that didn't have a formal def in MipsRegisterInfo.td would get flagged.
>
> !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
>
> % tblgen -gen-asm-matcher -I ~/workarea/asm/llvm/include/ Mips.td
> Included from Mips.td:24:
> Included from MipsInstrInfo.td:1120:
> Mips64InstrInfo.td:173:1: error: error: unable to find operand: 'zero'
> def DSDIV : Div64<M...
2016 Dec 15
2
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
...(ops i8imm, RC, i32imm);
> }
> def vx256xmem : X86VMemOperand<MSA128D, "printi256mem">;
>
> def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>;
>
> class LD_INDIRECT_DESC_BASE2<string instr_asm,
> RegisterOperand ROWD,
> RegisterOperand ROWSP = ROWD,
> InstrItinClass itin = NoItinerary> {
> dag OutOperandList = (outs ROWD:$wd, VK128Opnd:$wdm);
>...
2016 Mar 22
0
Immediate operand for load instruction, in back end
...got inspired from
> Mips' MSA SIMD
> extensions.)
> Could you please tell me what's the right way to do it?
>
>
> Here, the load class has $addrsrc which is a relative address with base a
> certain
> register and offset:
> class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
> ValueType TyNode, RegisterOperand ROWD,
> Operand MemOpnd = mem_msa,
> ComplexPattern Addr = addrimm10,
> InstrItinClass itin = NoItinerary> {
> dag OutOperandList = (outs ROWD:$wd);
> dag InOperandList = (ins MemOpnd:$addr...
2016 Dec 09
0
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hi Alex,
I don’t know too much about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need:
If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition.
It allows a PatFrag be passed into the avx512_gather multiclass definition.
2016 Dec 09
5
TableGen - Help to implement a form of gather/scatter operations for Mips MSA
Hello.
I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and
scatter operations exist for Mips, named LVI and SVI, respectively.
Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector
instructions) gather and scatter operations?
If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE,
but it