llvm dev - Dec 2016 - TableGen - Help to implement a form of gather/scatter operations for Mips MSA

Hello.
     I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that
gather and
scatter operations exist for Mips, named LVI and SVI, respectively.

     Did anyone think of implementing in the LLVM Mips back end (part of the MSA
vector
instructions) gather and scatter operations?
     If so, can you share with me the TableGen spec? (I tried to start from
LD_DESC_BASE,
but it doesn't seem to be trivial. Also, LLVM seems to have implemented
scatter/gather
instructions only for the x86 processor - there, they defined new SDNodes called
GatherNode and ScatterNode.)

   Thank you,
     Alex

Hi Alex,

I don’t know too much about recent MIPS, but have recently been doing something
similar for the new ARM SVE architecture, so hopefully this will get you closer
to what you need:

If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td),
‘GatherNode’ is a template argument, not a definition.
It allows a PatFrag be passed into the avx512_gather multiclass definition.

Working backwards from here, the actual PatFrags passed into this are things
like ‘mgatherv4i32’.  These are patterns that match a MaskedGatherSDNode for a
particular data type.

MaskedGatherSDNode is the generic SD node that represents a predicated gather,
which in turn was generated from Intrinsic::masked_gather in the IR (in
SelectionDAGBuilder::visitMaskedGather)

If your MIPS instruction has a predicate, you will need to create MIPS tablegen
that matches MaskedGatherSDNode.  If not, I guess you’ll need to create a new
intrinsic that represents an unpredicted gather, and add appropriate uses of it
during IR creation (such as in LoopVectorize, where masked gathers are created
today)

Hope that helps,

Will Lovett



On 9 December 2016 at 01:52:48, Alex Susu via llvm-dev (llvm-dev at
lists.llvm.org<mailto:llvm-dev at lists.llvm.org>) wrote:

Hello.
I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather
and
scatter operations exist for Mips, named LVI and SVI, respectively.

Did anyone think of implementing in the LLVM Mips back end (part of the MSA
vector
instructions) gather and scatter operations?
If so, can you share with me the TableGen spec? (I tried to start from
LD_DESC_BASE,
but it doesn't seem to be trivial. Also, LLVM seems to have implemented
scatter/gather
instructions only for the x86 processor - there, they defined new SDNodes called
GatherNode and ScatterNode.)

Thank you,
Alex
_______________________________________________
LLVM Developers mailing list
llvm-dev at lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
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Hello.
     Will, thanks a lot for pointing me to the MaskedGatherSDNode and
mgatherv4i32. I have
to say that the definition of the "multiclass avx512_gather" from 
lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use
it.

     I currently have some serious problems with TableGen - it gives an
assertion failure:
"llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2153: llvm::TreePatternNode* 
llvm::TreePattern::ParseTreePattern(llvm::Init*, llvm::StringRef): Assertion 
`New->getNumTypes() == 1 && "FIXME: Unhandled"'
failed."

     Can somebody help me with the code below responsible for this error?

     // From llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
     def mgatherv128i16 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
       (masked_gather node:$src1, node:$src2, node:$src3) , [{
       if (MaskedGatherSDNode *mgNode = dyn_cast<MaskedGatherSDNode>(N))
         return (mgNode->getIndex().getValueType() == MVT::v128i16 ||
                 mgNode->getBasePtr().getValueType() == MVT::v128i16);
       return false;
     }]>;

     foreach RegId = 0-31 in
         def Mask#RegId : MipsReg<0, "Mask"#RegId>,
DwarfRegNum<[!add(RegId, 10)]>;
     def VK128: RegisterClass<"Connex", [v128i1], 32, (sequence
"Mask%u", 0, 31)>;
     def VK128Opnd : RegisterOperand<VK128> {
       let ParserMatchClass = MSA128AsmOperand;
     }

     class LD_INDIRECT_DESC_BASE2<string instr_asm,
                     ValueType TyNode,
                     RegisterOperand ROWD,
                     RegisterOperand ROWSI = ROWD,
                     RegisterOperand ROWSP = ROWD, // passthru register
                     InstrItinClass itin = NoItinerary> {
       dag OutOperandList = (outs ROWD:$wd);
       dag InOperandList = (ins ROWSP:$wsp, VK128Opnd:$wsm, ROWSI:$wsptr,
ROWSI:$wsi);
       string AsmString = "$wd = LS[R($wsi )];";
       list<dag> Pattern = [(set ROWD:$wd, (TyNode (masked_gather
ROWSP:$wsp, VK128Opnd
:$wsm, ROWSI:$wsptr, ROWSI:$wsi)))];
       InstrItinClass Itinerary = itin;
       string DecoderMethod = "DecodeMSA128Mem";
     }
     class LD_INDIRECT_D_DESC2 : LD_INDIRECT_DESC_BASE2<"read",
v128i16, MSA128DOpnd>;
     class LD_INDIRECT_D_ENC2 : MSA_2R_FMT<0b101001110>;
     def LD_INDIRECT_D2: LD_INDIRECT_D_ENC2, LD_INDIRECT_D_DESC2;

     /*
     // From http://llvm.org/docs/doxygen/html/SelectionDAGNodes_8h_source.html:
         02115   // In the both nodes address is Op1, mask is Op2:
         02116   // MaskedGatherSDNode  (Chain, src0, mask, base, index), src0
is a
passthru value
         02117   // MaskedScatterSDNode (Chain, value, mask, base, index)
         02118   // Mask is a vector of i1 elements
         02119   const SDValue &getBasePtr() const { return getOperand(3); }
         02120   const SDValue &getIndex()   const { return getOperand(4); }
         02121   const SDValue &getMask()    const { return getOperand(2); }
         02122   const SDValue &getValue()   const { return getOperand(1); }
// Alex: this
is pass-thru

     */


   Thank you very much,
     Alex

On 12/9/2016 4:18 PM, Will Lovett wrote:
> Hi Alex,
>
> I don’t know too much about recent MIPS, but have recently been doing
something similar
> for the new ARM SVE architecture, so hopefully this will get you closer to
what you need:
>
> If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td),
‘GatherNode’
> is a template argument, not a definition.
> It allows a PatFrag be passed into the avx512_gather multiclass definition.
>
> Working backwards from here, the actual PatFrags passed into this are
things like
> ‘mgatherv4i32’.  These are patterns that match a MaskedGatherSDNode for a
particular data
> type.
>
> MaskedGatherSDNode is the generic SD node that represents a predicated
gather, which in
> turn was generated from Intrinsic::masked_gather in the IR
> (in SelectionDAGBuilder::visitMaskedGather)
>
> If your MIPS instruction has a predicate, you will need to create MIPS
tablegen that
> matches MaskedGatherSDNode.  If not, I guess you’ll need to create a new
intrinsic that
> represents an unpredicted gather, and add appropriate uses of it during IR
creation (such
> as in LoopVectorize, where masked gathers are created today)
>
> Hope that helps,
>
> Will Lovett
>
>
> On 9 December 2016 at 01:52:48, Alex Susu via llvm-dev (llvm-dev at
lists.llvm.org
> <mailto:llvm-dev at lists.llvm.org>) wrote:
>
>> Hello.
>> I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf
that gather and
>> scatter operations exist for Mips, named LVI and SVI, respectively.
>>
>> Did anyone think of implementing in the LLVM Mips back end (part of the
MSA vector
>> instructions) gather and scatter operations?
>> If so, can you share with me the TableGen spec? (I tried to start from
LD_DESC_BASE,
>> but it doesn't seem to be trivial. Also, LLVM seems to have
implemented scatter/gather
>> instructions only for the x86 processor - there, they defined new
SDNodes called
>> GatherNode and ScatterNode.)
>>
>> Thank you,
>> Alex
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

Hi Alex,
> On 9 Dec 2016, at 01:52, Alex Susu via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> 
>  Hello.
>    I read on page 4 of
https://urldefense.proofpoint.com/v2/url?u=http-3A__www.cs.fsu.edu_-7Ewhalley_cda5155_chap4.pdf&d=CwIGaQ&c=Hw-EJUFt2_D9PK5csBJ29kRV40HqSDXWTLPyZ6W8u84&r=OWKUiguzzd2_T_K4Ka0qDEQ1sz6uNXO3VsbQDbiA6R8&m=qBOLs4N_Wqx6PzrOly6PAZyiapHyxBMIhn3E9OkjYjc&s=oukhOwlS56XWO6LLHzfUbAUVUvWNyAQ4nEcCxOOqeCs&e=
that gather and scatter operations exist for Mips, named LVI and SVI,
respectively.
The title of slide 4 is 'Extending the MIPS to Support Vector
Operations' and slide 6 mentions VMIPS so I think you may be looking at a
VMIPS specific extension of the MIPS ISA. VMIPS appears to be an implementation
of the R3000 that's intended as a teaching tool. Does your MIPS CPU have
this extension?
>    Did anyone think of implementing in the LLVM Mips back end (part of the
MSA vector instructions) gather and scatter operations?
Simon Dardis would be able to confirm but there aren't any as far as I know.
The closest I can think of is in MSA where you can get a similar effect with a
sequence of ld.df's and vshf.df's (or pck*.df's, ilv*.df's, etc.
for some of the common cases).
>    If so, can you share with me the TableGen spec? (I tried to start from
LD_DESC_BASE, but it doesn't seem to be trivial. Also, LLVM seems to have
implemented scatter/gather instructions only for the x86 processor - there, they
defined new SDNodes called GatherNode and ScatterNode.)
> 
>  Thank you,
>    Alex
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

Hi Alex,

The operations you refer to are part of an extension to MIPS called VMIPS for
teaching purposes.

The MIPS MSA ASE does not define vector scatter/gather instructions. As Daniel
points out in his reply, it's
possible to simulate vector scatter/gather operations through combinations of
shuffles, interleaves or just plain
GPR loads/stores combined with cross register bank copies.

I haven't looked at implementing any sort of vector scatter/gather style
optimizations for MIPS yet.

Thanks,
Simon
________________________________________
From: llvm-dev [llvm-dev-bounces at lists.llvm.org] on behalf of Alex Susu via
llvm-dev [llvm-dev at lists.llvm.org]
Sent: 09 December 2016 01:52
To: llvm-dev
Subject: [llvm-dev] TableGen - Help to implement a form of gather/scatter
operations for Mips MSA

   Hello.
     I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that
gather and
scatter operations exist for Mips, named LVI and SVI, respectively.

     Did anyone think of implementing in the LLVM Mips back end (part of the MSA
vector
instructions) gather and scatter operations?
     If so, can you share with me the TableGen spec? (I tried to start from
LD_DESC_BASE,
but it doesn't seem to be trivial. Also, LLVM seems to have implemented
scatter/gather
instructions only for the x86 processor - there, they defined new SDNodes called
GatherNode and ScatterNode.)

   Thank you,
     Alex
_______________________________________________
LLVM Developers mailing list
llvm-dev at lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

Hello.
     Daniel, Simon, I need to specify gather and scatter operations for our
research SIMD
processor that uses TableGen specs inspired heavily from the Mips (MSA) back
end.
     Although Mips currently does not have gather and scatter operations it is
an
interesting feature to have in mind, given also the fact that Mips has a very
clean
TableGen specification.
     As far as I can see, currently only x86 (and some non-official ARM
versions) have
gather and scatter operations.

     Now, it seems that I managed to do the TableGen for gather rather well, but
now I
face problems at instruction selection - I don't understand why it starts
splitting some
constant vectors as I described in the previous email (and also why the back end
fills a
constant vector's 2nd half with undefs, when it shouldn't).

   Thank you,
     Alex


On 12/12/2016 11:35 AM, Daniel Sanders wrote:
> Hi Alex,
>
>> On 9 Dec 2016, at 01:52, Alex Susu via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
>>
>>
>>  Hello.
>>    I read on page 4 of
https://urldefense.proofpoint.com/v2/url?u=http-3A__www.cs.fsu.edu_-7Ewhalley_cda5155_chap4.pdf&d=CwIGaQ&c=Hw-EJUFt2_D9PK5csBJ29kRV40HqSDXWTLPyZ6W8u84&r=OWKUiguzzd2_T_K4Ka0qDEQ1sz6uNXO3VsbQDbiA6R8&m=qBOLs4N_Wqx6PzrOly6PAZyiapHyxBMIhn3E9OkjYjc&s=oukhOwlS56XWO6LLHzfUbAUVUvWNyAQ4nEcCxOOqeCs&e=
that gather and scatter operations exist for Mips, named LVI and SVI,
respectively.
>
> The title of slide 4 is 'Extending the MIPS to Support Vector
Operations' and slide 6 mentions VMIPS so I think you may be looking at a
VMIPS specific extension of the MIPS ISA. VMIPS appears to be an implementation
of the R3000 that's intended as a teaching tool. Does your MIPS CPU have
this extension?
>
>>    Did anyone think of implementing in the LLVM Mips back end (part of
the MSA vector instructions) gather and scatter operations?
>
> Simon Dardis would be able to confirm but there aren't any as far as I
know. The closest I can think of is in MSA where you can get a similar effect
with a sequence of ld.df's and vshf.df's (or pck*.df's,
ilv*.df's, etc. for some of the common cases).
>
>>    If so, can you share with me the TableGen spec? (I tried to start
from LD_DESC_BASE, but it doesn't seem to be trivial. Also, LLVM seems to
have implemented scatter/gather instructions only for the x86 processor - there,
they defined new SDNodes called GatherNode and ScatterNode.)
>>
>>  Thank you,
>>    Alex
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>