search for: immsext16x

Displaying 9 results from an estimated 9 matches for "immsext16x".

2017 Feb 15
4
Unsigned int displaying as negative
I see. If I put simm16 and immSExt16x in place of uimm16 and immZExt16x respectively, the imm matches but it prints out -32768 (which is invalid for sub16u). We are using uimm16 not match unsigned but for PrintMethod, effectively uimm16 and simm16 are both Operand<i16>. I'm still unclear why simm16 matches and uimm16 does not...
2017 Feb 15
5
Unsigned int displaying as negative
...be: > > defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, > GPRRegs, DSTRegs, i16, i16, i16, uimm16, immZExt16x>; > > On Wed, Feb 15, 2017 at 2:37 PM, Ryan Taylor <ryta1203 at gmail.com> > wrote: > >> I see. If I put simm16 and immSExt16x in place of uimm16 and >> immZExt16x >> respectively, the imm matches but it prints out -32768 (which is >> invalid >> for sub16u). We are using uimm16 not match unsigned but for >> PrintMethod, >> effectively uimm16 and simm16 are both Operand<i16>. I...
2017 Feb 15
2
Unsigned int displaying as negative
Thanks for your reply. We are propagating sign info to tablegen currently using BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm. I imagine (I have not looked) they are printed according to instruction in AsmPrinter.cpp (pure speculation). I'm still confused as to why 0x7FFF is ok to match 16 bit int but not 0x8000? Thanks. On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...cA)), addr16:$dstD)]>; def MEM_MEM : SetADIn<asmstr, memhx, memhx, [(directStore (dstType (OpNode (srcAType (load addr16:$srcA)))), addr16:$dstD)]>; } defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, i16, i16, simm16, immSExt16x>; On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > Quentin, > > 1. I'll take a look, it's also picking the reg class by the > SimpleValueType and then getting the common subclass. Choosing to constrain > the reg class to GPRRegs inste...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...def MEM_MEM : SetADIn<asmstr, memhx, memhx, > [(directStore (dstType (OpNode (srcAType > (load addr16:$srcA)))), addr16:$dstD)]>; > } > > defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, > i16, i16, simm16, immSExt16x>; > > > What is defining VReg? > It is AD or is it MOV16Copy? > > Also what are the arguments of the multiclass AD that you match? > > > On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > >> Quentin, >> >> 1. I...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...lt;asmstr, memhx, memhx, >> [(directStore (dstType (OpNode (srcAType >> (load addr16:$srcA)))), addr16:$dstD)]>; >> } >> >> defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, >> i16, i16, simm16, immSExt16x>; >> >> >> What is defining VReg? >> It is AD or is it MOV16Copy? >> >> Also what are the arguments of the multiclass AD that you match? >> >> >> On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: >> >&...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...>>> [(directStore (dstType (OpNode (srcAType >>> (load addr16:$srcA)))), addr16:$dstD)]>; >>> } >>> >>> defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, GPRBaseRegs, >>> i16, i16, simm16, immSExt16x>; >>> >>> >>> What is defining VReg? >>> It is AD or is it MOV16Copy? >>> >>> Also what are the arguments of the multiclass AD that you match? >>> >>> >>> On Tue, Aug 25, 2015 at 1:02 PM, Ryan Taylor <ryta1203 at...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...[(directStore (dstType (OpNode (srcAType >>>> (load addr16:$srcA)))), addr16:$dstD)]>; >>>> } >>>> >>>> defm MOV16Copy_ : AD<"mov16", null_frag, GPRBaseRegs, >>>> GPRBaseRegs, i16, i16, simm16, immSExt16x>; >>>> >>>> >>>> What is defining VReg? >>>> It is AD or is it MOV16Copy? >>>> >>>> Also what are the arguments of the multiclass AD that you match? >>>> >>>> >>>> On Tue, Aug 25, 2015 at...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the