search for: imm16

...he commit that added support for it <http://lists.cs.uiuc.edu/pipermail/llvm-branch-commits/2010-May/003229.html>. I'm not sure I understand the distinction between retl/retq. x86 has 4 return instruction (cribbing from the Intel manual): C3 RET Near return CB RET Far return C2 iw RET imm16 Near return + pop imm16 bytes CA iw RET imm16 Far return + pop imm16 bytes (And I think that's been true since the 8086.) Distinguishing between near and far (e.g., ret vs. lret in AT&T or retn vs. retf with some other assemblers) makes sense, but what would a l or q suffix denote? But m...

...generation in a (new) Z80 backend: The CPU has a couple of 8 bit physical registers, e.g. H, L, D and E, which are overlaid in 16 bit register pairs named HL and DE. It has also a native instruction to load a 16 bit immediate value into a 16 bit register pair (HL or DE), e.g.: LD HL,<imm16> Now when having a sequence of loading two 16 bit register pairs with the *same* immediate value, the simple approach is: LD HL,<imm16> LD DE,<imm16> However, the second line can be shortened (in opcode bytes and cycles) to load the overlaid 8 bit registers of HL (H an...

...MyInst<ops, asmstr, pattern, itin> { let Inst{31-28} = OpcVal{31-28}; bits<6> Rsrc1; <===== Because destination is required first in operand ordering, bits<6> Rdest; <===== this ordering of declarations produces an incorrect GenCodeEmitter bits<16> Imm16; let Inst{27-22} = Rsrc1; let Inst{21-16} = Rdest; let Inst{15-0} = Imm16; } def ORI : MyFormat<0, (ops GPRegs:$Rdest, GPRegs:$Rsrc1, i32imm: $Imm16), ... In the generated emitter (wrong): Rsrc1 <- MI.Operand(0) Rdest <- MI.Operand(1); However, there would be quite a bit of...

...idth integers: I can extract from our architecture description language ISAC code, that for each instruction tells what it does: Syntax: MIPS instrucion ADDDI "ADDI" reg(0) "," reg(1) "," imm(2) Semantics: unsigned int gpregs[32]; void instr_direct_rri$op_addi$imm16$() { int op_arithm_imm = 0x08; { int rt = 1; { int rs = 28; { short imm16 = imm_i16(2); //--- intrinsics, represents instruction's immediate operand { { int simm = ((int)(imm16) << (32 - (16))) >> (32 - (16)); switch (op_arithm_imm) { //.... case 0x08: case 0x09: {if (rt != 0) g...

Hi Adam, John is right, the TCE stuff would be useful for you. Our compiler targets a processor template that the designer can populate pretty freely. The compiler then reads the architecture description and creates an LLVM backend on the fly. Please don't hesitate to get in touch with us if you have questions. -- Pertti

On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > I noticed that the TableGen code emitter generator assumes that the > instruction fields are declared in the instruction format in the > same order that operands are defined. This seems like a bad > dependence to me, and that TableGen should match the name of field > declared in the instruction with the name of the

Hello gyus, I am working on a project, where we are trying to create a development environment for new ASIP processor design. Part of this project is a compiler generator, where we would like to generate C compiler from some instruction description. To keep it short, let's say, that in each instruction's semantics is described by some C code. What I would like to do is to compile this

Hi Adam, > One problem, I was trying to solve was, that I need to declare variables of let's say 5-bit width like 'i5 var', > the maximal bit-width may be limited to 64 bits. I need such variables to represent instruction's operands, > example is at the end this message. any standard compliant C compiler supports i5, believe it or not. Try this: #include

I noticed that the TableGen code emitter generator assumes that the instruction fields are declared in the instruction format in the same order that operands are defined. This seems like a bad dependence to me, and that TableGen should match the name of field declared in the instruction with the name of the operand in order to determine which operand of the MI to use . See

...CPU has a couple of 8 bit physical registers, e.g. H, L, D and > E, which are overlaid in 16 bit register pairs named HL and DE. > > It has also a native instruction to load a 16 bit immediate value > into a 16 bit register pair (HL or DE), e.g.: > > LD HL,<imm16> > > Now when having a sequence of loading two 16 bit register pairs > with the *same* immediate value, the simple approach is: > > LD HL,<imm16> > LD DE,<imm16> > > However, the second line can be shortened (in opcode bytes and &gt...

Hello everyone. I'm not an expert neither in llvm nor in x86 nor in IEEE standard for floating point numbers, thus any of my following assumptions maybe wrong. If so, I will be grateful if you clarify me what's goes wrong. But if my guesses are correct we possibly have a bug in fp arithmetics on x86. I have the following ir: @g = constant i64 1 define i32 @main() { %gval = load

...erand Imm:1000>> I still get the 8-bit variant instead of LDAi16oPC, and the operand is truncated. The TableGen-generated .inc file has { 444 /* lda */, MC6809::LDAi8oPC, Convert__imm_95_0__Imm81_0, AMFBS_None, { MCK_Imm8, MCK_PC }, }, { 444 /* lda */, MC6809::LDAi16oPC, Convert__imm_95_0__Imm161_0, AMFBS_None, { MCK_Imm16, MCK_PC }, }, ... so how do I get the 16-bit variant with MCK_Imm16 selected instead? The instructions are defined as def LDAi8oPC : MC6809LoadIndexed_i8oPC_P1< (outs GR8:$dst8), (ins pcoffset8:$offset), !strconcat(&q...

...r and, if the decremented value is not zero, jumps (with a relative jump) to a given offset. I've described in tablegen this instruction as follow: def DECJNZ : Instruction { let Namespace = "MyTarget"; let OutOperandList = (outs GprRegs:$R0); let InOperandList = (ins GprRegs: $R1, imm16:$dest); let AsmString = "DECJNZ $R0, $dest"; let isBranch = 1; let isTerminator = 1; let Constraints = "$R1 = $R0"; let Defs = [SR]; } I would like to create an optimization pass to make countable loops faster by using this instruction. The simplest loop that I would like to...

...e TargetInstrInfo.td file should be like: at first I am defining the class form my instruction: *class Mymov<bits&lt;6> op, string instr_asm>: FI<op, (outs Regs1:$rs), (ins Regs2:$rt), !strconcat(instr_asm, &quot;\t$rt, $rs&quot;), [], NoItinerary> { let imm16 = 0; }* where *Regs1* and *Regs2* are corresponding *RegisterClasses*. Then I need to define the instruction: *def MOVInstr : Mymov<0x2, "mov">;* *def : TargetPat<(int_myintrinsicname), (MOVInstr)>;* /// error: In anonymous.4: Instruction 'MOVInstr' expects more op...

...is not zero, jumps (with a relative jump) to a given offset. > > I've described in tablegen this instruction as follow: > > def DECJNZ : Instruction { > let Namespace = "MyTarget"; > let OutOperandList = (outs GprRegs:$R0); > let InOperandList = (ins GprRegs: $R1, imm16:$dest); > let AsmString = "DECJNZ $R0, $dest"; > let isBranch = 1; > let isTerminator = 1; > let Constraints = "$R1 = $R0"; > let Defs = [SR]; > } > > I would like to create an optimization pass to make countable loops faster by > using this instructio...

...!strconcat("lw", "$dst, $c($b)"), [/* ??? what goes here? */]>; // load immediate def LLOri : ImmediateFormat <0b110001, (outs DLXRegs:$dst), (ins i32imm:$b), !strconcat("llo", "$dst, $b"), [(set DLXRegs:$dst, (lo16 imm16:$b))]>; def LHIri : ImmediateFormat <0b110000, (outs DLXRegs:$dst), (ins i32imm:$b), !strconcat("llo", "$dst, $b"), [(set DLXRegs:$dst, (hi16 imm16:$b))]>; ** DLXInstrInfo.td ********************************************************* //===- DLX.t...

Hi, *case MICROBLAZE::BGEID:* * {* * // op: raencoder* * op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);* * Value |= (op & UINT64_C(31)) << 16;* * // op: imm16* * op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); -> should be operand[1]* * Value |= op & UINT64_C(65535);* * break;* * }* I have added different encoder method for operand(1) but that operand is not even propagated in Encodeinstruction.. by the way,t...

...elative jump) to a given offset. >> >> I've described in tablegen this instruction as follow: >> >> def DECJNZ : Instruction { >> let Namespace = "MyTarget"; >> let OutOperandList = (outs GprRegs:$R0); >> let InOperandList = (ins GprRegs: $R1, imm16:$dest); >> let AsmString = "DECJNZ $R0, $dest"; >> let isBranch = 1; >> let isTerminator = 1; >> let Constraints = "$R1 = $R0"; >> let Defs = [SR]; >> } >> >> I would like to create an optimization pass to make countable loops fast...

On Tue, Mar 17, 2015 at 6:14 PM, Tim Northover <t.p.northover at gmail.com> wrote: >> As a simplification, the compiler deals almost exclusively in pseudo >> instructions. By x86 analogy, using pseudos to unfold a TEST32rm into >> MOV32rm + TEST32rr means I can skip the complex operand fitting effort >> needed to pick specific machine instructions. There are many

...TOS. Or DX for INS. RawFrmDstSrc - Instruction uses SI/ESI/RSI as a source memory address and DI/EDI/RDI as a destination memory address. MOVS and CMPS instructions. RawFrmImm8 - Rare instruction that has two immediates. The first is 8-bits the second one is controlled by ImmT field. RawFrmImm16 - Rare instruction that has two immediates. The first is 16-bits the second one is controlled by ImmT field. MRMDestMem - modrm.mod!=0x3, modrm[2:0] and optional sib byte and displacement encode destination memory address. vex.vvvv is used encodes the next register, modrm[5:3] encodes desti...