Displaying 9 results from an estimated 9 matches for "il_op_mov".
2011 Dec 16
2
[LLVMdev] Vector immediates in tablegen w/o build_vector?
I have two patterns in tablegen that do look like the exact same thing:
Pat 1)
def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
(ins i16imm:$val),
asm, [(set GPRV4I16:$dst, (build_vector (i16 imm:$val)))]>;
Pat 2)
def v4i16imm : Operand<v4i16>;
def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
(ins v4i16imm:$val),
asm, [(set GPRV4I16:$dst, (v4i16 imm:$val)...
2008 Oct 06
1
[LLVMdev] sign extensions on loads?
...de:$ptr), [{
return isGenericLoad(dyn_cast<LoadSDNode>(N));
}]>;
def ADDRf : ComplexPattern<i32, 2, "SelectADDRf", [frameindex], []>;
// Load Memory Operations
multiclass LOADm<string asm, PatFrag OpNode, ComplexPattern addr> {
def _i32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
asm, [(set (i32 GPR:$dst), (OpNode addr:$ptr))]>;
def _f32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
asm, [(set (f32 GPR:$dst), (OpNode addr:$ptr))]>;
def _i64 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins ME...
2011 Mar 31
3
[LLVMdev] Assert in VerifySDNode
...t;IL_vextract>;
// Class that handles the various vector extract patterns
multiclass VectorExtract<SDNode OpNode> {
...
def _v4i32 : ExtractVectorClass<GPRI32, GPRV4I32, OpNode>;
...
}
class ExtractVectorClass<RegisterClass DReg, RegisterClass SReg, SDNode OpNode>
: ILFormat<IL_OP_MOV, (outs DReg:$dst), (ins SReg:$src0, i32imm:$src1),
"mov $dst, $src0",
[(set DReg:$dst, (OpNode SReg:$src0, timm:$src1))]>;
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";...
2011 Sep 13
3
[LLVMdev] Setting priority in instruction selection
...;IL_OP_BFI, (outs GPRI32:$dst),
(ins GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat),
!strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
[(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs, GPRI32:$bitpat))]>;
and also this instruction:
def LOADCONST_i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
(ins i32imm:$val),
"mov $dst, $src",
[(set GPRI32:$dst, imm:$val)]>;
Now, what is happening with this code, (A & B) | (C & ~B), where B is an immedate and ~B is an inverse of it,
instead of getting
LOADCONST_i32 r0 B
BFI_i32 r1, A, C, r...
2008 Sep 23
1
[LLVMdev] Tablegen strings
I have a tablegen string that I want to add a modifier to the registers
that are being matched.
For example a simple match on fneg:
def FNEG : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins
GPR:$src0),
"mov $dst, $src0", [(set GPR:$dst, (fneg GPR:$src0))]>;
I want to place a modifier directly after $src0 in the string so that no
space is between the string
and the matched register. I.e. I want to generate "mov $dst, $src0_neg"...
2008 Sep 23
2
[LLVMdev] Store patterns accepting i32 only?
...ILISD::GLOBAL_STORE", SDTStore,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def global_store : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
return isGlobalStore(dyn_cast<StoreSDNode>(N));
}]>;
def GLOBALSTORE : OneInOneOut<IL_OP_MOV, (outs), (ins GPR:$val,
MEM:$ptr),
"mov g[$ptr], $val",
[(global_store GPR:$val, ADDR:$ptr)]>;
I want this same pattern to be able to accept all the types for val that
GPR is mapped to(i32, i64, f32, f64).
Is there any way I can mo...
2011 Sep 13
0
[LLVMdev] Setting priority in instruction selection
...GPRI32:$rhs, GPRI32:$bitpat),
>
> !strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
>
> [(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs,
> GPRI32:$bitpat))]>;
>
> and also this instruction:
>
>
>
> def LOADCONST_i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
>
> (ins i32imm:$val),
>
> "mov $dst, $src",
>
> [(set GPRI32:$dst, imm:$val)]>;
>
>
>
>
>
> Now, what is happening with this code, (A & B) | (C & ~B), where B is an
> immedate and ~B is an inverse o...
2011 Sep 13
1
[LLVMdev] Setting priority in instruction selection
...strconcat(IL_OP_BFI.Text, " $dst, $lhs, $rhs, $bitpat"),
> >
> > [(set GPRI32:$dst, (bfi_pat1 GPRI32:$lhs, GPRI32:$rhs,
> > GPRI32:$bitpat))]>;
> >
> > and also this instruction:
> >
> >
> >
> > def LOADCONST_i32 : ILFormat<IL_OP_MOV, (outs GPRI32:$dst),
> >
> > (ins i32imm:$val),
> >
> > "mov $dst, $src",
> >
> > [(set GPRI32:$dst, imm:$val)]>;
> >
> >
> >
> >
> >
> > Now, what is happening with this code, (A & B) | (C &...
2008 Sep 23
0
[LLVMdev] Store patterns accepting i32 only?
...;, SDTStore,
> [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
>
> def global_store : PatFrag<(ops node:$val, node:$ptr),
> (st node:$val, node:$ptr), [{
> return isGlobalStore(dyn_cast<StoreSDNode>(N));
> }]>;
> def GLOBALSTORE : OneInOneOut<IL_OP_MOV, (outs), (ins GPR:$val, MEM:
> $ptr),
> "mov g[$ptr], $val",
> [(global_store GPR:$val, ADDR:$ptr)]>;
>
> I want this same pattern to be able to accept all the types for val
> that GPR is mapped to(i32, i64, f32, f64)...