llvm dev - Mar 2011 - [LLVMdev] Assert in VerifySDNode

We are syncing to 2.9 and we are hitting an with our backend in VerifySDNode in
SelectionDAG.cpp.
The first assert here is failing
  assert(!isa<MemSDNode>(N) && "Bad MemSDNode!");

Now, this is new to 2.9 and I am trying to understand what is invalid about what
I am generating.
What I generate has worked fine from LLVM version 2.4 until now without causing
any issues.

This is occuring while I am attempting to lower a vector extract elt to a custom
SDNode that my backend understands.
I am creating the instruction like as follows:
Op = DAG.getNode(AMDILISD::VEXTRACT,
        Op.getDebugLoc(), Op.getValueType(),
        Op.getOperand(0),
       
DAG.getTargetConstant(dyn_cast<ConstantSDNode>(Op.getOperand(1)->getZExtValue()
+ 1), MVT::i32));

The custom backend instruction is defined as follows:
def SDTIL_GenVecExtract : SDTypeProfile<1, 2, [
    SDTCisEltOfVec<0, 1>, SDTCisVT<2, i32>
    ]>;
def IL_vextract   : SDNode<"AMDILISD::VEXTRACT",
SDTIL_GenVecExtract>;

defm VEXTRACT         : VectorExtract<IL_vextract>;
// Class that handles the various vector extract patterns
multiclass VectorExtract<SDNode OpNode> {
...
def _v4i32 : ExtractVectorClass<GPRI32, GPRV4I32, OpNode>;
...
}
class ExtractVectorClass<RegisterClass DReg, RegisterClass SReg, SDNode
OpNode>
: ILFormat<IL_OP_MOV, (outs DReg:$dst), (ins SReg:$src0, i32imm:$src1),
     "mov $dst, $src0",
     [(set DReg:$dst, (OpNode SReg:$src0, timm:$src1))]>;
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag>
pattern>
: Instruction {
     let Namespace = "AMDIL";
     dag OutOperandList = outs;
     dag InOperandList = ins;
     ILOpCode operation = op;
     let Pattern = pattern;
     let AsmString = !strconcat(asmstr, "\n");
     bit hasIEEEFlag = 0;
     bit hasZeroOpFlag = 0;
}

I cannot see how I am doing anything wrong here. I've looked at the
equivalent x86 shuffle
instructions and they don't look that much different. The big difference is
they do not
specify the SDTCisEltOfVec constraint.

Any ideas?

Thanks,
Micah
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So I have debugged into my problem w/ VerifySDNode more  to try to figure out
why this is occuring and I ran across another peculiarity.

I have a intrinsic that reads from a special register a vec4 i32 value.
The intrinsic is specified as:
def int_AMDIL_get_global_id :
GCCBuiltin<"__amdil_get_global_id_int">,
      Intrinsic<[llvm_v4i32_ty], [], []>;

My pattern for the intrinsic is:
def GET_GLOBAL_ID : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
      (ins), !strconcat(IL_OP_MOV.Text, " $dst, r1021.xyz0"),
      [(set GPRV4I32:$dst, (int_AMDIL_get_global_id))]>;

There is no problem here and works fine.

However if I do this:
def int_AMDIL_get_global_id :
GCCBuiltin<"__amdil_get_global_id_int">,
      Intrinsic<[llvm_v4i32_ty], [], [IntrNoMem]>;

Then my pattern fails and my intrinsic has two extra arguments(Entry Token and
some constant value which I am guessing is the intrinsic opcode).

Does anyone have an idea of what would cause IntroNoMem to stop my pattern from
being matched? It isn't just this intrinsic, any intrinsic I add it to no
longer matches. If I remove the field, it matches correctly.

Thanks,
Micah
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Hi Micah,
> assert(!isa<MemSDNode>(N) && "Bad MemSDNode!");
you can't use getNode to allocate a MemSDNode because it does not allocate
enough memory (MemSDNode has extra fields beyond the operands).

Ciao, Duncan.

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
> On Behalf Of Duncan Sands
> Sent: Thursday, March 31, 2011 7:43 PM
> To: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Assert in VerifySDNode
> 
> Hi Micah,
> 
> > assert(!isa<MemSDNode>(N) && "Bad
MemSDNode!");
> 
> you can't use getNode to allocate a MemSDNode because it does not
> allocate
> enough memory (MemSDNode has extra fields beyond the operands).
> 
[Villmow, Micah] Duncan, thanks for the reply. But I don't see how I am
generating a MemSDNode with this instruction.
> Ciao, Duncan.
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