search for: i64imm

...class REP_1R_DESC_BASE<, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); /* From include/llvm/Target/Target.td: let OperandType = "OPERAND_IMMEDIATE" in { ... def i64imm : Operand<i64>; */ dag InOperandList = (ins i64imm:$imm); string AsmString = "REPEAT_X_TIMES($imm"; list<dag> Pattern = [(int_repeat_x_times i64imm:$imm)]; InstrItinClass Itinerary = itin; } class REP_D_DESC : REP_...

Hi Alex, On 5 December 2016 at 18:00, Alex Susu <alex.e.susu at gmail.com> wrote: > We can compile it. Note that this is the only compilable code w.r.t. > using i64 or i64imm (in the 2 lines above: "dag InOperandList", "list<dag> > Pattern"). Yeah, you actually want to use "imm": list<dag> Pattern = [(int_repeat_x_times imm:$imm)]; When the table generator sees "i64" it doesn't go looking in the InOperand...

But don't the defs for ADDR_RR and ADDR_RI also contain dags? def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; Do I need to create some other intermediate node type for a shifted address? Phil On Mon, Sep 26, 2016 at 1:42 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 9/26/2016 3:36 PM, Phil Tomson via llvm-dev wrote: > >> def ADDR_SH...

...[SDTCisInt<0>, SDTCisInt<1>]>; def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; let Constraints = "$dst = $addr" in { //, Uses= [GRP] in { def RelAddr : XSTGPseudo< (outs GPRC:$dst), (ins i64imm:$spoff, i64imm:$addr), "! RELADDR $spoff, $dst", [(set GPRC:$dst, (XSTGRELADDR i64:$spoff, (i64 (XSTGMVINI i64:$addr))...

...: SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; let Constraints = "$dst = $addr", Uses= [GRP] in { def RelAddr : XSTGPseudo< (outs GPRC:$dst), //(ins GPRC:$spoff, GPRC:$addr), (ins i64imm:$spoff, i64imm:$addr), "! RELADDR $spoff, $dst", [(set GPRC:$dst, (XSTGRELADDR i64:$spoff, (XSTGMVINI i64:$addr) ) )]&g...

...in this table: http://ref.x86asm.net/coder32.html 2. Insert an instruction into lib/Target/X86/X86InstrInfo.td using this opcode. In this case, I used 0xF1, and created the following instruction: def CACHE_OPERAND_B64i : RIi64<0xF1, AddRegFrm, (outs GR64:$unused), (ins i64imm:$b), "cache_operand_b_i64\t$b", [(int_cache_operand_b_i64 i64imm:$b)]>, Requires<[In64BitMode]>; However, when I compile, I'm getting errors of the form: Error: Primary decode conflict: TEST64ri32 would overwrite CACHE_OPERAND_B64i ModRM 19...

...DDR_RR and ADDR_RI also contain dags? >> >> def ADDR_RR : Addr< 2, "SelectAddrRegReg", >> (ops GPRC:$base, GPRC:$offsetreg) >; >> def ADDR_RI : Addr< 2, "SelectAddrRegImm", >> (ops GPRC:$base, i64imm:$offsetimm) >; >> >> Do I need to create some other intermediate node type for a shifted >> address? >> > > Technically yes, but the list of allowed types is limited. "RegisterClass" > (e.g GPRC) is allowed, as is "Operand" (e.g. i64imm). >...

...gt; diff --git a/lib/Target/BPF/BPFInstrInfo.td b/lib/Target/BPF/BPFInstrInfo.td > index f683578..56f0f9c 100644 > --- a/lib/Target/BPF/BPFInstrInfo.td > +++ b/lib/Target/BPF/BPFInstrInfo.td > @@ -464,7 +464,7 @@ let usesCustomInserter = 1 in { > (ins GPR:$lhs, i64imm:$rhs, i64imm:$imm, > GPR:$src, GPR:$src2), > "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2", > [(set i64:$dst, > - (BPFselectcc i64:$lhs, (i64 imm:$rhs), (i64 > imm:$imm), i64:$src, i64:$src2))]>...

...MIOperandInfo = opInfo; } let PrintMethod = "printMemOperand" in { def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; def ADDR_SHLI : Addr< 2, "SelectAddrShlImm", (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >; } If I change the LoadOpIdx definition to: class LoadOpIdx< bits<7> op, string instr_asm, Ope...

Hi, I've tagged the 5.0.1-rc2 release, go ahead and start testing and report your results. -Tom

...def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; >> >> >> let Constraints = "$dst = $addr" in { //, Uses= [GRP] in { >> def RelAddr : XSTGPseudo< (outs GPRC:$dst), >> (ins i64imm:$spoff, i64imm:$addr), >> "! RELADDR $spoff, $dst", >> [(set GPRC:$dst, (XSTGRELADDR >> i64:$spoff, >> >> (i64 (XSTGMVINI i64:$addr)) >>...

Hi Jiangning, On Apr 15, 2014, at 11:12 PM, Jiangning Liu <liujiangning1 at gmail.com> wrote: > Hi Quentin, > > Thanks for your feedback! >> ​ARM64 generates pseudo instructions ARM64::MOVaddr and friends in ISEL stage, which intends to guarantee address serialization (page address + in-page address), and exposes adrp finally by pass ExpandPseudoInsts. The assumption of

Hi, All, I want to lower 64 Bits constant such as 'long' and 'double'. So I define them like this: def CONSTI64 : InstFOO<(outs GRWideRegs:$dst), (ins i64imm:$src), "const-long $dst, $src", [(set (i64 GRWideRegs:$dst), imm:$src)]>{ let isMoveImm = 1; } def CONSTF64 : InstFOO<(outs GRWideRegs:$dst), (ins f64imm:$src), "const-double $dst, $s...

You can tell LLVM that you have "sign extended" setCC results (all ones). Dan On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote: > On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah > <Micah.Villmow at amd.com> wrote: >> The IR produces correct results, but my backend does not and the >> only thing >> I can think of is that the IR is treating the

...e function whose name you provide will be used to > match the DAG and generate the output. > > The instruction definition would have 3 inputs: register, register and > immediate: > > def ADDR_SHLI: Addr<3, "SelectAddrShlImm", > (ops GPRC:$base, GPRC:$offsetreg, i64imm:$shift)>; > > The matching function would then need to match DAG and generate these 3 > values if the match succeeded. What I'm finding is that the matching function for 3 arguments (the SelectAddrShlImm) is never tried for this particular case. This one is tried: def ADDR_RR...

...icate) at index 162, continuing at 236 Match failed at index 246 Continuing at 263 LLVM ERROR: Cannot select: t16: ch = store<ST256[inttoptr (i16 250 to <128 x i16>*)]> t13:1, t13, Constant:i16<250>, undef:i16 because all my scalar memory operands are i64 or i64imm in the .td specification files. So I guess I need to change all scalar memory operands to i16 or i16imm in the .td specification files. Please let me know if you see a possibility to fix this problem I guess I should do something like: - // Inspired from ARMISelLowering.cpp: f...

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -

Hello LLVM Developers, We are working on extending currently available register rematerialization to include cases where sequence of multiple instructions is required to rematerialize a value. We had a discussion on this in community mailing list and link is here: http://lists.llvm.org/pipermail/llvm-dev/2016-September/subject.html#104777 >From the above discussion and studying the code we

...:$label), >> "$dst = CONST32($label)", >> [(set IntRegs:$dst, (HexagonCONST32 bbl:$label))]>; >> >> let isReMaterializable = 1, isMoveImm = 1 in >> -def CONST64_Int_Real : LDInst<(outs DoubleRegs:$dst), (ins i64imm:$global), >> +def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global), >> "$dst = CONST64(#$global)", >> [(set DoubleRegs:$dst, imm:$global) ]>; >> >> @@ -3046,3 +3046,7 @@ include &q...