search for: i40e

...e6 Mellanox NIC eth1 Intel NIC eth2 Intel NIC eth4 Intel NIC eth5 Intel NIC And bond1 still consist of eth0 and eth1, but eth1 is Intel NIC, instead of Mellanox NIC. Following is selected log from /var/log/messages: ... kernel: [ 23.098148] i40e: Intel(R) 40-10 Gigabit Ethernet Connection Network Driver - version 2.2.4 kernel: [ 23.098554] i40e: Copyright(c) 2013 - 2017 Intel Corporation. kernel: [ 23.114270] i40e 0000:1a:00.0: fw 3.1.57069 api 1.5 nvm 3.33 0x80000f09 255.65535.255 kernel: [ 23.118320] i40e 0000:1a:00.0:...

Hi I have a small question about NIC driver (e.g. i40e) loading. Who is responsible to load i40e driver? And how does he knows we should load i40e, instead of ixgbe? Thanks.

Duncan, here is part of the assembly around the problem area. I used gcc -S -flto to generate the .s file, llvm-as on the .s fiile will show error: invalid cast opcode for cast from 'i40' to 'float' %638 = trunc i40 %637 to float %633 = bitcast i8* %632 to float* %634 = bitcast float* %633 to i40* %635 = load i40* %634, align 1 %636 = shl i40 %635, 7 %637 = ashr i40

...ng list" <centos at centos.org> > Cc: > Subject: Re: [CentOS] Who is responsible to load NIC driver when boot up > > On Sat, Apr 27, 2019 at 11:44 PM wuzhouhui <wuzhouhui14 at mails.ucas.ac.cn> > wrote: > > > I have a small question about NIC driver (e.g. i40e) loading. Who is > > responsible to load i40e driver? And how does he knows we should load > > i40e, instead of ixgbe? > > > `depmod` may put hardware/driver lists into initramfs when `mkinitrd` is > called when a new kernel is installed. > Also check file: /lib/modules...

Hi ZY, On 11/05/13 22:21, Zhiyuan Ren wrote: > Duncan, > > here is part of the assembly around the problem area. I used gcc -S -flto to > generate the .s file, llvm-as on the .s fiile will show error: invalid cast > opcode for cast from 'i40' to 'float' %638 = trunc i40 %637 to float > > %633 = bitcast i8* %632 to float* > %634 = bitcast float* %633 to

On Dec 2, 2009, at 12:32 PM, Ken Dyck wrote: > Would there be any interest/opposition to extending the set of simple > integer types in MVT to include the missing multiples of 8 (up to 64 > bits)? That is: i24, i40, i48, i56? > > Adding the types to MVT (and ValueTypes.td) would allow LLVM to be > targeted to architectures that have registers and operations of these > sizes

On Wednesday, December 02, 2009 7:09 PM, Chris Lattner wrote: > > On Dec 2, 2009, at 12:32 PM, Ken Dyck wrote: > > > Would there be any interest/opposition to extending the set > of simple > > integer types in MVT to include the missing multiples of 8 > (up to 64 > > bits)? That is: i24, i40, i48, i56? > > > > Adding the types to MVT (and

...Enhancement Advisory 2016:0464 Upstream details at : https://rhn.redhat.com/errata/RHEA-2016-0464.html The following updated files have been uploaded and are currently syncing to the mirrors: ( sha256sum Filename ) x86_64: c24738b7d58cc0a24d4ba2bb6ff090bb641fa0f12bcc0e7f31ffcc2cc3a6e773 kmod-i40e-1.3.21_k-1.el7_2.x86_64.rpm Source: 867a83ca723b110a44c2aca41b39cd373751a44ac6ae1d17336ffaca02b5c3e8 i40e-1.3.21_k-1.el7_2.src.rpm -- Johnny Hughes CentOS Project { http://www.centos.org/ } irc: hughesjr, #centos at irc.freenode.net Twitter: @JohnnyCentOS

...Enhancement Advisory 2016:1394 Upstream details at : https://rhn.redhat.com/errata/RHEA-2016-1394.html The following updated files have been uploaded and are currently syncing to the mirrors: ( sha256sum Filename ) x86_64: 38665ae0af8a8192bebd09c5f624f7acf95a07b8ab6197ae20766c79c327ad9a kmod-i40e-1.5.10_k-1.el7_2.x86_64.rpm Source: 05c0b3ff6a502a50a80a5024fcb158604723884cd8e5dddfcc40001420a021cb i40e-1.5.10_k-1.el7_2.src.rpm -- Johnny Hughes CentOS Project { http://www.centos.org/ } irc: hughesjr, #centos at irc.freenode.net Twitter: @JohnnyCentOS

...Enhancement Advisory 2016:1902 Upstream details at : https://rhn.redhat.com/errata/RHEA-2016-1902.html The following updated files have been uploaded and are currently syncing to the mirrors: ( sha256sum Filename ) x86_64: eb2c140f5b95878b359ca8c65274ea3b73020ddb3b4b797ed4f8499d332d4822 kmod-i40e-1.5.10_k-2.el7_2.x86_64.rpm Source: dd03d63ea0ec326bd696d5512605e6e9976d28dd09727a00f51c02080d6af1b8 i40e-1.5.10_k-2.el7_2.src.rpm -- Johnny Hughes CentOS Project { http://www.centos.org/ } irc: hughesjr, #centos at irc.freenode.net Twitter: @JohnnyCentOS

...ment Advisory 2017:1388 Upstream details at : https://rhn.redhat.com/errata/RHEA-2017-1388.html The following updated files have been uploaded and are currently syncing to the mirrors: ( sha256sum Filename ) x86_64: fc4079f76e3fb6e8d1fce4f0320b7d426d31d97abe170e0cd8c271e6b03ffc9b kmod-redhat-i40e-1.6.27_k_dup7.3-1.el7_3.x86_64.rpm Source: 7f4a6d484065c10c89d2f5e23ba6517eddd512174d70bcb560b48234f074f65e kmod-redhat-i40e-1.6.27_k_dup7.3-1.el7_3.src.rpm -- Johnny Hughes CentOS Project { http://www.centos.org/ } irc: hughesjr, #centos at irc.freenode.net Twitter: @JohnnyCentOS

...cement Advisory 2018:0579 Upstream details at : https://access.redhat.com/errata/RHEA-2018:0579 The following updated files have been uploaded and are currently syncing to the mirrors: ( sha256sum Filename ) x86_64: 973726f539d915e4d6667bcd4a551f08403e56307c00ed85032ac916e5414982 kmod-redhat-i40e-2.1.14_k_dup7.4-2.1.el7_4.x86_64.rpm c5deeb12aef29bff75a15fbf3af2d09acfd97841f64ef5a8596c4bbf09712052 kmod-redhat-i40evf-3.0.1_k_dup7.4-2.1.el7_4.x86_64.rpm Source: ef9a7cd89dea97c47b17796bb25546cb9cbc5dd11a28e74b70af8b3ec5f81a9e kmod-redhat-i40e-2.1.14_k_dup7.4-2.1.el7_4.src.rpm 9f5eb3e913cba0b...

Hi All, I have a Quantum scalar i40 tape library. I need to configure it to TWO tape partition libraries, e.g., library_a and library_b, so that each library has its own tape drive. Then connect this physical tape library to two different CentOS servers so that each server can see its own media changer and tape drive. I once had a successful configuration on one host but NOT on the other. One

Would there be any interest/opposition to extending the set of simple integer types in MVT to include the missing multiples of 8 (up to 64 bits)? That is: i24, i40, i48, i56? Adding the types to MVT (and ValueTypes.td) would allow LLVM to be targeted to architectures that have registers and operations of these sizes (for example, a 24-bit DSP that I'd like to develop a back end for has 24-,

Duncan, Is there a way (switch) for embedding original source code in the generated .s file? thanks, ZY On Sun, May 12, 2013 at 4:12 AM, Duncan Sands <baldrick at free.fr> wrote: > Hi ZY, > > > On 11/05/13 22:21, Zhiyuan Ren wrote: > >> Duncan, >> >> here is part of the assembly around the problem area. I used gcc -S -flto >> to >> generate

Hi ZY, On 11/05/13 20:37, Zhiyuan Ren wrote: > Duncan, > > Thanks for getting back to me. I am not sure how to find the original bitcode > (and related Ada source code) that causes the truncate. This is the error > message that gcc gave me when I tried to compile an Ada source file using > dragonegg plugin (gcc -c -fplugin...). use -S instead of -c and add -flto The resulting

Hi all! Our target (a non-public DSP) has 40-bit integer registers, and our C front-end support 40-bit integers (ie our LLVM assembler use i40 types). It seems as every native type should be added as a Machine Value Type (MVT). However, it also seems to be required that each SimpleValueType enum in MVT has a bit-width that is a power of 2. Do any of you have ideas how to add support for

Hi Ken, > Would there be any interest/opposition to extending the set of simple > integer types in MVT to include the missing multiples of 8 (up to 64 > bits)? That is: i24, i40, i48, i56? the type legalizer would need some work. Consider an architecture which has a 24 bit register. Then the type legalizer should legalize an i40 by first promoting it to an i48, then expanding that to

Duncan, Thanks for getting back to me. I am not sure how to find the original bitcode (and related Ada source code) that causes the truncate. This is the error message that gcc gave me when I tried to compile an Ada source file using dragonegg plugin (gcc -c -fplugin...). ZY ps, sorry for multiple emails, trying to find out how to reply to a thread in the mailing list On Sat, May 11, 2013 at

Hi all, I recently created a version of llvm/clang for an architecture with some odd properties: - front end side: -- char,short,int : 20 bits -- long, long long: 40 bits -- pointer: 20 bits On the backend side, I have hardware support for 20-bit registers (and load/stores). (So, I have support for 'i20' and 'i40', but 'i40' is lowered into operations on 'i20')