Displaying 20 results from an estimated 33 matches for "huang2".
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2010 Oct 07
31
[RFC][QEMU] ATI graphics VBIOS passthru support
...passthru mode. The guest VM system BIOS (including Windows boot logo) can now show in passthru screen. We have tested with various Windows and Linux guest VMs. Please help review it. We are also looking forward to comments and suggestions from Xen community users.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Wei Wang <wei.wang2@amd.com>
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2007 Mar 22
2
[PATCH][HAP][2/2] fix CR4 initialization when hap is on
This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being
constructed under nested paging mode. It complies with recent
reset_to_realmode change in hvmloader.
Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com>
)
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2008 May 09
14
[PATCH] patch to support super page (2M) with EPT
Attached are the patches to support super page with EPT. We only support
2M size. And shadow may still work fine with 4K pages.
The patches can be split into 3 parts. Apply order is as attached.
tool.diff
To allocate 2M physical contiguous memory in guest except the first 2M
and the last 2M.
The first 2M covers special memory, and Xen use the last few pages in
guest memory to do special
2012 Mar 23
7
LWP Interrupt Handler
I am adding interrupt support for LWP, whose spec is available at
http://support.amd.com/us/Processor_TechDocs/43724.pdf. Basically OS can
specify an interrupt vector in LWP_CFG MSR; the interrupt will be
triggered when event buffer overflows. For HVM guests, I want to
re-inject this interrupt back into the guest VM. Here is one idea
similar to virtualized PMU: It first registers a special
2007 Sep 13
3
Hardware Assisted Paging Param and Message
This patch changes hap parameter from boolean to integer. So users can
disable and enable hap using "hap=0" and "hap=1". It also prints out
nested paging message under SVM.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
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2011 Jan 31
9
[PATCH][SVM] Fix 32bit Windows guest VMs save/restore
...incorrect values and shouldn''t be used
for save/restore. This patch checks the LMA bit of EFER register in the
save/restore code path.
Please apply it to both Xen-4.0 and Xen-unstable trees.
Reported-by: James Harper <james.harper@bendigoit.com.au>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Acked-by: Christoph Egger <christoph.egger@amd.com>
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2010 Dec 15
5
[PATCH] svm: support VMCB cleanbits
...can be re-used from the previous
VMRUN instruction.
Each bit represents a certain set of fields in the VMCB.
Setting a bit tells the cpu it can re-use the cached value
from the previous VMRUN.
Clearing a bit tells the cpu to reload the values from the given VMCB.
Signed-off-by: Wei Huang <Wei.Huang2@amd.com>
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
Christoph
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---to satisfy European Law for business letters:
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Einsteinring 24, 85609 Dornach b. Muenchen
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2011 Jan 11
6
[RFC PATCH 0/2] ASID: Flush by ASID
...supports a new feature called flush by ASID. The idea is to
allow CPU to flush TLBs associated with the ASID assigned to guest VM. So
hypervisor doesn''t have to reassign a new ASID in order to flush guest''s
VCPU. Please review it.
Thanks,
Wei
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Wei Wang <wei.wang2@amd.com>
--
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Sitz: Dornach, Gemeinde Aschheim,
Landkreis München Registergericht München,
HRB Nr. 43632
WEEE-Reg-Nr: DE 12919551
Geschäftsführer:
Alberto Bozzo, Andrew Bowd
__________________________________________...
2007 Apr 03
2
Question regarding the number of P2M l3e entries
In p2m.c (line 197 and line 550), the code assumes the number of L3 P2M
table entries is 8 (under PAE mode). According to Intel and AMD specs,
it is 4. Could someone explain this discrepancy? Is it a bug?
-Wei
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2010 Dec 22
0
[PATCH 2/2] xsave: extend xsave/xrstor support to all (64) features
...umps up
sub-leaves to 63.
2. It creates a common function for xsave.
3. The main leaf 0 of CPUID:0x0000000D in current Xen is broken,
especially ECX and EBX registers. This patch cleans it up.
4. It adds support to detects EBX value of CPUID:0x0000000D main leaf 0
on-the-fly.
Signed-off-by: Wei Huang2 <wei.huang2@amd.com>
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2007 Mar 26
3
[PATCH] pciback: restore PCI BARs on D3->D0 transition
Ever since xen-unstable cset 14308 ("pci back: Fix registration of of
filters on subsections of config space") I''ve been getting an MCA on the
*2nd* boot of a driver domain using an e1000 NIC. Cset 14308 allowed
the proper setup of the PM control registers, so the NIC is put in the
D3 power state when the driver domain shuts down. Unfortunately,
pci_set_power_state()
2011 Feb 07
0
[xen-unstable test] 5665: regressions - FAIL
...p <george.dunlap@eu.citrix.com>
Ian Jackson <ian.jackson@eu.citrix.com>
Juergen Gross <juergen.gross@ts.fujitsu.com>
Keir Fraser <keir@xen.org>
Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Stephen Smalley <sds@tycho.nsa.gov>
Wei Huang <wei.huang2@amd.com>
Wei Wang <wei.wang2@amd.com>
------------------------------------------------------------
jobs:
build-i386-xcpkern pass
build-amd64 fail
build-i386...
2006 Oct 19
0
[HVM][SVM][PATCH][1/2] VINTR intercept signal
...y check of RFLAGS.IF for ExtInt injection.
These apply cleanly to xen-unstable c/s 11831.
Please apply to xen-unstable.hg.
We would also want these patches to be in a 3.0.3-1 base whenever that
is branched.
Signed-off-by: Travis Betak <travis.betak@amd.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Tom Woller <thomas.woller@amd.com>
--Tom
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2006 May 30
0
[PATCH][SVM] CPUID cleanup
...ort.
Keir,
Can those 2 patches KY posted last week, also be applied to 3.0.2?
We''ve booted 64bit SUSE10 8-way, and 64bit RHEL4u3 4-way, BigSMP SUSE,
and largeSMP RHEL kernels with these 3 patches.
Signed-off-by: Tom Woller <thomas.woller@amd.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Tom
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2007 Jan 25
0
[PATCH][PAGING][P2M][1/1] Common Interface for P2M table
...2. Intel VT boxes:
* 32-bit PAE Xen: 32-bit SUSE10, 32-bit WinXP SP2, 32b SUSE 10 PAE
BigSMP, and 32-bit Windows 2003 Enterprise
* 64-bit Xen: 32-bit WinXP SP2, 32-bit Windows 2003 enterprise, 32-bit
SUSE10, 32-bit SUSE10 PAE BigSMP, and 64Bit RHEL 4
Signed-off-by: Wei Huang <Wei.Huang2@amd.com>
arch/x86/domain.c | 2
arch/x86/mm/shadow/common.c | 714
++++---------------------------------------
arch/x86/mm/shadow/private.h | 21 -
arch/x86/mm/shadow/types.h | 4
arch/x86/paging.c | 601
++++++++++++++++++++++++++++++++++++
include/asm-x86/...
2010 Dec 03
0
[PATCH 1/1] svm: dump VMCB physical address
VMCB physical address is useful for hardware debug. This small patch
dumps VMCB physical address.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
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2011 Jan 11
1
[RFC PATCH 2/2] ASID: Flush by ASID
This patch implements flush by asid feature for AMD CPUs.
Thanks,
Wei
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Wei Wang <wei.wang2@amd.com>
--
Advanced Micro Devices GmbH
Sitz: Dornach, Gemeinde Aschheim,
Landkreis München Registergericht München,
HRB Nr. 43632
WEEE-Reg-Nr: DE 12919551
Geschäftsführer:
Alberto Bozzo, Andrew Bowd
__________________________________________...
2011 Apr 14
0
[PATCH][RFC] FPU LWP 5/5: enable LWP CPUID for HVM guests
This patch enables LWP related CPUID to HVM guests.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
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2006 Oct 19
2
[HVM][SVM][PATCH][2/2] Delay ExtInt Injection
...ecessary check of RFLAGS.IF for ExtInt injection.
Applies cleanly to xen-unstable c/s 11831.
Please apply to xen-unstable.hg.
We would also want this patch to be in a 3.0.3-1 base whenever that is
branched.
Signed-off-by: Travis Betak <travis.betak@amd.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Tom Woller <thomas.woller@amd.com>
--Tom
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2008 Apr 21
2
[Patch][RFC] Super Page Patch
The attached file is the super page patch which supports both 2MB and
4MB (depending on the paging modes of hypervisor) under hardware
assisted paging. The idea is to allocate super pages when guests are
being created. Whenever such requests cannot be satisfied, it falls back
to normal 4KB allocation. Also it splits large pages into normal 4KB
pages whenever necessary. This patch is applicable on