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...on call with an ISD::FSQRT SDNode. If I remove the above test, then the compiler will emit a sqrtsd instruction. I am hoping that someone might be able to comment on what onlyReadsMemory is supposed to do be doing in general and why it is returning false in this case. Thanks! Preston -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130517/051b48de/attachment.html>

...he movl. If you are familiar with the Post-RA scheduler works, then I would appreciate any suggestions you might have as to how I could fix this problem, such as by treating inline assembly code as a barrier or by including memory references in scheduling decisions. Thanks, Preston G -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121017/0ef31365/attachment.html> -------------- next part -------------- A non-text attachment was scrubb...

...Info Entry, then using the extracted code in a switch statement to print out the operands for a particular class of instruction. Would you know if there is a way, given a MachineInstr, to obtain the address offset? Or, if not, could you sketch out a way to do that? Thanks, Preston -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP

...not aware that the value in XMM0 is implicitly consumed by the RET instruction. Could one of you tell me where in the LLVM source code I should be looking to find where function return registers are set up such that the critical anti-dependency code can notice them? Thanks, Preston -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP

On 21.05.2013, at 23:03, "Gurd, Preston" <preston.gurd at intel.com> wrote: > Thanks for the fix! > > However, there still seems to be a problem in that if you pass –ffast-math to clang, then clang changes “sqrt” to be “__sqrt_finite”. LLVM cannot then change the function call into an x86 sqrt instruction...

On May 17, 2013, at 3:33 PM, "Gurd, Preston" <preston.gurd at intel.com> wrote: > Using the following example program > > #include <math.h> > > double f(double d){ > return sqrt(d); > } > > and compiling it with “clang –O3 …”, I was trying to determine what it would take to get th...

...e that the new scheduler be made to run after register allocation is done, as has already been discussed in LLVMDev. Please let me know what the next step should be. Preston -----Original Message----- From: Andrew Trick [mailto:atrick at apple.com] Sent: Friday, September 20, 2013 2:02 AM To: Gurd, Preston Cc: Hal Finkel; llvm commits Subject: Re: [llvm] r190717 - Adds support for Atom Silvermont (SLM) - -march=slm Hi Preston, On Sep 17, 2013, at 4:01 PM, Gurd, Preston <preston.gurd at intel.com> wrote: > Hello Andy, > > Why do you say below that there is "no reason t...

...RAX in transforming the SUBREG_TO_REG pseudo op into a MOV32rr, liveness checking fails in MachineVerifier.cpp. Would anyone be able to comment on why the SUBREG_TO_REG conversion changes the destination register and/or to suggest how this problem might best be fixed? Thanks! Preston -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120726/2ceaa157/attachment.html>

Thanks for the fix! However, there still seems to be a problem in that if you pass –ffast-math to clang, then clang changes “sqrt” to be “__sqrt_finite”. LLVM cannot then change the function call into an x86 sqrt instruction, even with –fno-math-errno set. Can you suggest where I might look in the clang code to find the place where “sqrt” is converted to “__sqrt_finite” and/or the best way to

...t version does not do so. Is this optimization the kind of thing that the bb-vectorizer is intended to be able to do? And, if so, do you have any suggestions as to how that may be done? Or, if not, can you suggest another possible way to parallelize this kind of code? Thanks, Preston -- Preston Gurd <preston.gurd at intel.com> Intel Waterloo -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120228/014cce40/attachment.html>

-- Preston Gurd <preston.gurd at intel.com> Intel Waterloo SSG/DPD/ECDL/DMP -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120409/b78a88d6/attachment.html>

On Nov 20, 2008, at 8:31 AM, Preston Gurd wrote: > Might you instead consider just adding a -disable-mmx option? I agree, this is a better approach. This distinguishes between capabilities of the chip and the desire to codegen specific vectors one way or another. -Chris > > Preston > > On Thu, 2008-20-11 at 02:57 -0...

Does fast-math imply no-math-errno ? Thanks, Nadav On May 17, 2013, at 15:36, Chris Lattner <clattner at apple.com> wrote: > > On May 17, 2013, at 3:33 PM, "Gurd, Preston" <preston.gurd at intel.com> wrote: > >> Using the following example program >> >> #include <math.h> >> >> double f(double d){ >> return sqrt(d); >> } >> >> and compiling it with “clang –O3 …”, I was trying...

Might you instead consider just adding a -disable-mmx option? Preston On Thu, 2008-20-11 at 02:57 -0500, Mon Ping Wang wrote: > Hi, > > When setting -mattr option on X86, I would like to treat MMX > separately from SSE levels. This would allow a client who sets the > attributes directly to set the SSE level independent of MMX, e.g., llc > -march=x86 -mattr=sse41, one would get

-----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of John Criswell Sent: Tuesday, September 11, 2012 1:42 PM To: Steve Checkoway Cc: LLVMdev at cs.uiuc.edu Subject: Re: [LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass ... > >> The code for adding the 32-bit instruction is: >> >>

Hi, When setting -mattr option on X86, I would like to treat MMX separately from SSE levels. This would allow a client who sets the attributes directly to set the SSE level independent of MMX, e.g., llc -march=x86 -mattr=sse41, one would get sse4.1 with mmx disabled while llc -march=x86 -mattr=mmx -mattr=sse42 will get mmx and sse42. If anyone objects to this change, please let me

The output of the avx-hadd program is 3 11 7 15 Preston -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands Sent: Thursday, September 22, 2011 3:14 PM To: Bruno Cardoso Lopes Cc: LLVMdev Subject: Re: [LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits Hi Bruno, > Some comments: