search for: gpreg

...d for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPRegs, GPRegs); let EncoderMethod = "getMemEncoding"; } def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; def LDRAM : FG1<0b000001, (outs GPRegs:$dst), (ins mem:$src), "ldram $dst,$src", [(set GPRegs:$dst, (load addr:$src))]>;...

...to be able to infer integer types in patterns that it was able to before, but I'm not clear on why that's the case. This isn't just the results of instructions, but also immediate values as well. It seems to affect a smattering of node types. Any insights? For instance: where GPRegs contains types [i32, f32] def BEQ : IF8<Opc.BEQ, (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), "beq $Rsrc1, $Rsrc2, $SImm16", [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: $SImm16)], s_br>; Tablegen reports: BEQ: (br...

...in patterns that it was able to > before, but I'm not clear on why that's the case. ok > This isn't just the results of instructions, but also immediate > values as well. It seems to affect a smattering of node types. Any > insights? > > For instance: > > where GPRegs contains types [i32, f32] > > def BEQ : IF8<Opc.BEQ, > (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), > "beq $Rsrc1, $Rsrc2, $SImm16", > [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: > $SImm16)], s_br>; >...

...add C0, C1, C2, C3, C4, C5, C6, C7)>; // C7 = constant one and by expanding SELECT_CC to SETCC and BR_CC to BRcond. In my IntstrInfo description, I have the following patterns: //cmp (setcc) instruction def CMPri : F1<0b0000001101, (outs CondRegs:$cd), (ins GPRegs:$rn, uimm8:$uimm8), "c7 cmp\tne, $cd, $rn, $uimm8", [(set CondRegs:$cd, (setne GPRegs:$rn, uimmZExt8:$uimm8))]>; //conditional branch def BRcondrel : F3_1<0b011110, (outs), (ins CondRegs:$cd, brtarget:$offset), "$cd br\t$offset", [(brcond Co...

...Example of why do I need arbitrary bit-width integers: I can extract from our architecture description language ISAC code, that for each instruction tells what it does: Syntax: MIPS instrucion ADDDI "ADDI" reg(0) "," reg(1) "," imm(2) Semantics: unsigned int gpregs[32]; void instr_direct_rri$op_addi$imm16$() { int op_arithm_imm = 0x08; { int rt = 1; { int rs = 28; { short imm16 = imm_i16(2); //--- intrinsics, represents instruction's immediate operand { { int simm = ((int)(imm16) << (32 - (16))) >> (32 - (16)); switch (op_arithm_imm) { //...

...re, but I'm not clear on why that's the case. > > ok > >> This isn't just the results of instructions, but also immediate >> values as well. It seems to affect a smattering of node types. Any >> insights? >> >> For instance: >> >> where GPRegs contains types [i32, f32] >> >> def BEQ : IF8<Opc.BEQ, >> (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), >> "beq $Rsrc1, $Rsrc2, $SImm16", >> [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: >> $S...

...terns that it > was able to before, but I'm not clear on why that's the case. > > This isn't just the results of instructions, but also immediate > values as well. It seems to affect a smattering of node types. Any > insights? > > For instance: > > where GPRegs contains types [i32, f32] > > def BEQ : IF8<Opc.BEQ, > (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), > "beq $Rsrc1, $Rsrc2, $SImm16", > [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: > $SImm16)], s_br>; >...

Hi Adam, John is right, the TCE stuff would be useful for you. Our compiler targets a processor template that the designer can populate pretty freely. The compiler then reads the architecture description and creates an LLVM backend on the fly. Please don't hesitate to get in touch with us if you have questions. -- Pertti

Hi Adam, > One problem, I was trying to solve was, that I need to declare variables of let's say 5-bit width like 'i5 var', > the maximal bit-width may be limited to 64 bits. I need such variables to represent instruction's operands, > example is at the end this message. any standard compliant C compiler supports i5, believe it or not. Try this: #include

Hello gyus, I am working on a project, where we are trying to create a development environment for new ASIP processor design. Part of this project is a compiler generator, where we would like to generate C compiler from some instruction description. To keep it short, let's say, that in each instruction's semantics is described by some C code. What I would like to do is to compile this

...ine, but then the register allocator and coalescer are resisting coalescing the COPY MI's for various reasons - for example, the read-only register class contains too few registers and the live range threshold cancels the coalescing. A simple example (post-ISEL): %vreg2<def> = COPY %C1; GPReg:%vreg2 ... %vreg11<def> = MUL %vreg7, %vreg2; GPreg:%vreg11,%vreg7,%vreg2 I'd want it to propagate %C1 into the MUL, replacing %vreg2. How is this supposed to work? Is there a DAG operation or MF pass that should handle this before regalloc, or some other means? Thanks, Joe ------------...

...e destination is required first in operand ordering, bits<6> Rdest; <===== this ordering of declarations produces an incorrect GenCodeEmitter bits<16> Imm16; let Inst{27-22} = Rsrc1; let Inst{21-16} = Rdest; let Inst{15-0} = Imm16; } def ORI : MyFormat<0, (ops GPRegs:$Rdest, GPRegs:$Rsrc1, i32imm: $Imm16), ... In the generated emitter (wrong): Rsrc1 <- MI.Operand(0) Rdest <- MI.Operand(1); However, there would be quite a bit of renaming required to get the instruction format fields to match up with the MI operand names for all the back ends that...

...-end for LLVM where any instruction may take any type of data. I am looking for the output to be of the format: inst.type reg1,reg2 etc. Where inst is the instruction, e.g. mov and type is data-type e.g. f32 etc. I tried creating a back-end with a register class which could take i32 and f32: def GPRegs : RegisterClass <"Test", [i32,f32], // Formats supported by this class 32, // Memory alignment [ R0, R1, R2, R3, R4 ] .... And then used this class in the patterns for the instructions. However, I couldn't get this to work...

On Apr 18, 2007, at 11:25 AM, Christopher Lamb wrote: > I noticed that the TableGen code emitter generator assumes that the > instruction fields are declared in the instruction format in the > same order that operands are defined. This seems like a bad > dependence to me, and that TableGen should match the name of field > declared in the instruction with the name of the

I noticed that the TableGen code emitter generator assumes that the instruction fields are declared in the instruction format in the same order that operands are defined. This seems like a bad dependence to me, and that TableGen should match the name of field declared in the instruction with the name of the operand in order to determine which operand of the MI to use . See

...IO_MultSrc<op0t, SpecialReg>.insDefault>; ... } multiclass TwoSrcOneDestSpec<bits<5> subOpcode, string opcodeStr> { defm _dds: MultSrc1Spec<subOpcode, 0b10, opcodeStr, SpecialReg>; ... defm _rr: MultSrc1Spec<subOpcode, 0b11, opcodeStr, GPReg>; } defm ADD : TwoSrcOneDestSpec<0b10000, "add">; I currently get the error "Undefined reference:'ADDanonymous_545'" when I try to generate. Any advice would be greatly appreciated, even if that advice is "don't try to conditionally set ins and out...

Hi everyone, I am trying to write a pass, that finds some instructions and replaces them with my intrinsics, but I am having problem understanding, how this should be done. Let's say I have this instruction: %tmp14 = load i32* getelementptr ([32 x i32]* @gpregs, i32 0, i64 28) and i need to read the load's operands and replace it by let's say: %tmp14 = call i32 @llvm.regread_i32.i32(i32 0, i32 1) Here is what I have: //for each instruction of a function for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I) { Instructi...

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