search for: getbaseptr

...es? If so, this would likely take care of the normal case if the POD is on the stack and writing patterns is a lot easier than custom selecting or lowering. Q2: Is there any way to determine a POD's offset based on a LoadSDNode and StoreSDNode's data? Currently, LoadSDNode::getBasePtr (and StoreSDNode::getBasePtr) can return something back, but how do I access the operand's offset (and hence, alignment) relative to a base register? Q3: There are three variants of load (and store) for the SPU. Two of the variants take 10- and 16-bit sign extended offsets, whe...

...toreSDNode. From looking at the SelectionDAGNodes header file, the only class that has the getValue function call is SrcValueSDNode that returns a Value type. The only class that has getType is a ConstantPoolSDNode. I don't think that ConstantPoolSDNode is what I want and when I try to cast the getBasePtr().Val of the StoreSDNode to a SrcValueSDNode it asserts on: Assertion failed: isa<X>(Val) && "cast<Ty>() argument of incompatible type!" This is what I'm attempting: SDValue LangTargetLowering::LowerSTORE(SDValue Op, SelectionDAG& DAG){ const StoreSD...

thanks for the help ..I do add the chain and the result. My code is like this ... SDValue Ops[] = { load->getChain(), load->getOperand(1), load->getBasePtr(), des }; DAG.getNode(CustomOpc, NodeTys, Ops, 4); thanks again! shrey On Thu, Nov 12, 2009 at 4:41 PM, Anton Korobeynikov <anton at korobeynikov.info> wrote: >> My problem is that the second call asserts inside legalize ops at >> ResultVals[Op.getResNo()]; b'cos Resul...

...leFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); } Is it in BUG or am I missing something? Thanks, Yaniv

Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions have something similar... MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MemOp[0] = cast<MemSDNode>(N)->getMemOperand(); ca...

...AG &DAG) { LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode()); ISD::LoadExtType ExtType = LD->getExtensionType(); if (LD->getExtensionType() == ISD::ZEXTLOAD) { DEBUG(errs() << "ZEXTLOAD\n"); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); DebugLoc dl = Op.getNode()->getDebugLoc(); SDValue LdResult = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32, Chain, Ptr, LD->getPointerInfo(), MVT::i32, LD->isVolatile(), LD->isNonTemporal(),...

...Hi, > > During instruction selection, I have the following code for certain > LOAD instructions: > > const LoadSDNode *LD = cast<LoadSDNode>(N); > SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), > VT, PtrVT, MVT::Other, > LD->getBasePtr(), LD->getChain()); > > // Honestly, I have no idea what this does, but other memory > // accessing instructions have something similar... > MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); > MemOp[0] = cast<MemSDNode>(N)->getMem...

...6 : PatFrag<(ops node:$src1, node:$src2, node:$src3), (masked_gather node:$src1, node:$src2, node:$src3) , [{ if (MaskedGatherSDNode *mgNode = dyn_cast<MaskedGatherSDNode>(N)) return (mgNode->getIndex().getValueType() == MVT::v128i16 || mgNode->getBasePtr().getValueType() == MVT::v128i16); return false; }]>; foreach RegId = 0-31 in def Mask#RegId : MipsReg<0, "Mask"#RegId>, DwarfRegNum<[!add(RegId, 10)]>; def VK128: RegisterClass<"Connex", [v128i1], 32, (sequence "Mask%u&quot...

The address qualifier is stored in the type of %result. From that operand, you can get the Value and then call getType. The type for result should be a PointerType which you cast to a PointerType and get the getAddressSpace e.g. cast<PointerType>(Ty)->getAddressSpace() -- Mon Ping On Sep 17, 2008, at 1:06 PM, Villmow, Micah wrote: > How do I access the address qualifier

How do I access the address qualifier from the store instruction. Given the following code: define void @test_unary_op_anegate(float %x, float addrspace(11)* %result) nounwind { entry: %neg = sub float -0.000000e+000, %x ; <float> [#uses=1] store float %neg, float addrspace(11)* %result ret void } When I attempt to generate this code, I'm

The reason the ones in PPCInstrInfo.td don't have the patterns to match is the reason they are more analogous to your problem. Namely, tblgen does not have a way to produce nodes with more than one result. The load-with-update instructions do exactly that - one of the inputs is also an output, but the other output is independent (and necessarily a separate register). The FMA variants have

Hi Alex, I don’t know too much about recent MIPS, but have recently been doing something similar for the new ARM SVE architecture, so hopefully this will get you closer to what you need: If you’re looking where I think you are (lib/Target/X86/X86InstrAVX512.td), ‘GatherNode’ is a template argument, not a definition. It allows a PatFrag be passed into the avx512_gather multiclass definition.

Hi, I would like to know if it is possible to extract the source level names of variables that create loop-carried dependencies. For example, for the following code: for (int i = 0; i < A_ROW; i++) { for (int j = 1; j < B_COL; j++) { a_matrix[i][j] = a_matrix[i][j - 1]; } } I get the following AST: #pragma omp parallel for

...LR, DL, MVT::Glue, DAG.getConstant(7, DL, MVT::i8)); // Perform the nonatomic load. auto *Node = cast<AtomicSDNode>(AtomicOp.getNode()); SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(AtomicOp), AtomicOp.getValueType(), Node->getChain(), Node->getBasePtr(), Node->getMemoryVT(), Node->getMemOperand()); auto Restore = DAG.getCopyToReg(DAG.getEntryNode(), DL, AVR::SREG, Save); return Load; I can’t figure out how I can glue all these nodes together and return the nonatomic load. How can I do this? Cheers,...

...node:$src2, node:$src3), >> (masked_gather node:$src1, node:$src2, node:$src3) , [{ >> if (MaskedGatherSDNode *mgNode = dyn_cast<MaskedGatherSDNode>(N)) >> return (mgNode->getIndex().getValueType() == MVT::v128i16 || >> mgNode->getBasePtr().getValueType() == MVT::v128i16); >> return false; >> }]>; >> >> foreach RegId = 0-31 in >> def Mask#RegId : MipsReg<0, "Mask"#RegId>, DwarfRegNum<[!add(RegId, 10)]>; >> def VK128: RegisterClass<"Connex&...

...ops node:$src1, node:$src2, node:$src3), > (masked_gather node:$src1, node:$src2, node:$src3) , [{ > if (MaskedGatherSDNode *mgNode = dyn_cast<MaskedGatherSDNode>(N)) > return (mgNode->getIndex().getValueType() == MVT::v128i16 || > mgNode->getBasePtr().getValueType() == MVT::v128i16); > return false; > }]>; > > foreach RegId = 0-31 in > def Mask#RegId : MipsReg<0, "Mask"#RegId>, DwarfRegNum<[!add(RegId, 10)]>; > def VK128: RegisterClass<"Connex", [v128i1], 32, (se...

> My problem is that the second call asserts inside legalize ops at > ResultVals[Op.getResNo()]; b'cos ResultVals has only 1 element and > Op.resno is 0. Looks like you lowered the load improperly. It should return 2 values: the value loaded and a chain. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University

Hi I am running into a legalize dag issue after custom lowering a load. If someone can give me pointers that would be great. I am using llvm 2.6 When custom lowering a load, the following code gets executed. Tmp1 = TLI.LowerOperation(Tmp3, DAG); if (Tmp1.getNode()) { Tmp3 = LegalizeOp(Tmp1); Tmp4 = LegalizeOp(Tmp1.getValue(1)); <----------------- what

...termost loops are >> within the iteration) and finally again compare the indices of the >> dimension you are interested in. >> >> To finally get the array name, extract the ScopArrayInfo object >> pointer hidden in the user part of the tuple id. >> ScopArrayInfo::getBasePtr() gives you the array's base. For instance, >> it will be an llvm::Argument, but could also be any expression that >> computes the basepointer, eg. doesn't necessarily have a name from the >> source code. >> >> Michael >> >> >> >> 2016-0...

Hello. I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and scatter operations exist for Mips, named LVI and SVI, respectively. Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector instructions) gather and scatter operations? If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it