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Villmow, Micah

2008-Sep-17 20:06 UTC

[LLVMdev] store addrspace qualifier

How do I access the address qualifier from the store instruction.

Given the following code:

 

define void @test_unary_op_anegate(float %x, float addrspace(11)*
%result) nounwind  {

entry:

        %neg = sub float -0.000000e+000, %x             ; <float>
[#uses=1]

        store float %neg, float addrspace(11)* %result

        ret void

}

When I attempt to generate this code, I'm aborting on.

Cannot yet select: 017E8230: ch = store 017E7DF0, 017E8098, 017E8010,
017E81A8 <0035A078:0> alignment=4

So I am doing a custom Store function.

In my LowerStore function, I get an SDValue w/ opcode of 119(store) and
4 child Operands

Operand 0 is the entry token which I assume I can ignore

Operand 1 is the source data(%neg), which I finally can handle correctly
thanks to Eli

Operand 2 is the dst location with two children, an EntryToken and
Register(%result I'm guessing)

Operand 3 is undef

 

So, how do I find out the address space? The reason being different
address spaces are accessed with different registers.

 

Thanks,

 

Micah Villmow

Systems Engineer

Advanced Technology & Performance

Advanced Micro Devices Inc.

4555 Great America Pkwy,

Santa Clara, CA. 95054

P: 408-572-6219

F: 408-572-6596

 

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Mon Ping Wang

2008-Sep-17 22:45 UTC

head link

[LLVMdev] store addrspace qualifier

The address qualifier is stored in the type of %result.  From that  
operand, you can get the Value and then call getType.  The type for  
result  should be a PointerType which you cast to a PointerType and  
get the getAddressSpace e.g. cast<PointerType>(Ty)->getAddressSpace()

-- Mon Ping


On Sep 17, 2008, at 1:06 PM, Villmow, Micah wrote:
> How do I access the address qualifier from the store instruction.
> Given the following code:
>
> define void @test_unary_op_anegate(float %x, float addrspace(11)*  
> %result) nounwind  {
> entry:
>         %neg = sub float -0.000000e+000, %x             ; <float>  
> [#uses=1]
>         store float %neg, float addrspace(11)* %result
>         ret void
> }
> When I attempt to generate this code, I’m aborting on.
> Cannot yet select: 017E8230: ch = store 017E7DF0, 017E8098,  
> 017E8010, 017E81A8 <0035A078:0> alignment=4
> So I am doing a custom Store function.
> In my LowerStore function, I get an SDValue w/ opcode of 119(store)  
> and 4 child Operands
> Operand 0 is the entry token which I assume I can ignore
> Operand 1 is the source data(%neg), which I finally can handle  
> correctly thanks to Eli
> Operand 2 is the dst location with two children, an EntryToken and  
> Register(%result I’m guessing)
> Operand 3 is undef
>
> So, how do I find out the address space? The reason being different  
> address spaces are accessed with different registers.
>
> Thanks,
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P: 408-572-6219
> F: 408-572-6596
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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Villmow, Micah

2008-Sep-18 15:42 UTC

head link

[LLVMdev] store addrspace qualifier

Mon Ping, 

 Thanks for the tip, but I can't for the life of me seem to get the
Value from a StoreSDNode. From looking at the SelectionDAGNodes header
file, the only class that has the getValue function call is
SrcValueSDNode that returns a Value type. The only class that has
getType is a ConstantPoolSDNode. I don't think that ConstantPoolSDNode
is what I want and when I try to cast the getBasePtr().Val of the
StoreSDNode to a SrcValueSDNode it asserts on:

Assertion failed: isa<X>(Val) && "cast<Ty>() argument
of incompatible
type!"

 

This is what I'm attempting:

SDValue LangTargetLowering::LowerSTORE(SDValue Op, SelectionDAG& DAG){

    const StoreSDNode* storeOp = dyn_cast<StoreSDNode>(Op.Val);

    const SDValue& dstPtr    = storeOp->getBasePtr();

    const SrcValueSDNode* svdstVal = cast<SrcValueSDNode>(dstPtr.Val);

    const Value* dstVal = svdstVal->getValue();

    int addressSpace = ADDRESS_NONE;

    const Type* dstType = dstVal->getType();

    if (isa<PointerType>(dstType)) {

        const PointerType* ptrType = cast<PointerType>(dstType);

        addressSpace = ptrType->getAddressSpace();

    }

    printf("Addr: %d\n", addressSpace);

 SDValue Res;

  ....

  return Res;

}

 

Any idea what I'm doing wrong or how I can get this to work correctly?

 

Thanks,

Micah

________________________________

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Mon Ping Wang
Sent: Wednesday, September 17, 2008 3:45 PM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] store addrspace qualifier

 

 

The address qualifier is stored in the type of %result.  From that
operand, you can get the Value and then call getType.  The type for
result  should be a PointerType which you cast to a PointerType and get
the getAddressSpace e.g. cast<PointerType>(Ty)->getAddressSpace()

 

-- Mon Ping

 

 

On Sep 17, 2008, at 1:06 PM, Villmow, Micah wrote:





How do I access the address qualifier from the store instruction.

Given the following code:

 

define void @test_unary_op_anegate(float %x, float addrspace(11)*
%result) nounwind  {

entry:

        %neg = sub float -0.000000e+000, %x             ; <float>
[#uses=1]

        store float %neg, float addrspace(11)* %result

        ret void

}

When I attempt to generate this code, I'm aborting on.

Cannot yet select: 017E8230: ch = store 017E7DF0, 017E8098, 017E8010,
017E81A8 <0035A078:0> alignment=4

So I am doing a custom Store function.

In my LowerStore function, I get an SDValue w/ opcode of 119(store) and
4 child Operands

Operand 0 is the entry token which I assume I can ignore

Operand 1 is the source data(%neg), which I finally can handle correctly
thanks to Eli

Operand 2 is the dst location with two children, an EntryToken and
Register(%result I'm guessing)

Operand 3 is undef

 

So, how do I find out the address space? The reason being different
address spaces are accessed with different registers.

 

Thanks,

 

Micah Villmow

Systems Engineer

Advanced Technology & Performance

Advanced Micro Devices Inc.

4555 Great America Pkwy,

Santa Clara, CA. 95054

P: 408-572-6219

F: 408-572-6596

 

_______________________________________________
LLVM Developers mailing list
LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev



 

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