search for: getaddrspace

...> Date: Wed, 16 Sep 2015 16:25:29 +0000 > Subject: Re: [llvm-dev] How to add NOP? > To: erdemderebasoglu at hotmail.com; llvm-dev at lists.llvm.org > > Use MachineInstr::memoperands() function to get memory operands then you > can get the address space by using MachineMemOperand::getAddrSpace(). > > Volkan > > On Tue, Sep 15, 2015 at 11:40 PM Erdem Derebaşoğlu < > erdemderebasoglu at hotmail.com> wrote: > > Thanks for the response. How can I find out if an instruction uses a > private memory access? > > Erdem > ------------------------------ > F...

...o the translation. Thats perhaps not the cleanest implementation, but it would work. I was going to suggest that an alternative is to pass this information in to the load/store instructions in the backend, but it looks like that information is already available. That is, MachinePointerInfo has a getAddrSpace() method. This could potentially allow you to optimize MachineInstrs using the same knowledge you have here, e.g., constness for addrspace(3) in MachineLICM. > >> >> !address_spaces = !{!0, !1, !2, !3} >> >> ; Address space tuple. { address space number, parent addre...

...m From: vlknkls at gmail.com Date: Wed, 16 Sep 2015 16:25:29 +0000 Subject: Re: [llvm-dev] How to add NOP? To: erdemderebasoglu at hotmail.com; llvm-dev at lists.llvm.org Use MachineInstr::memoperands() function to get memory operands then you can get the address space by using MachineMemOperand::getAddrSpace(). Volkan On Tue, Sep 15, 2015 at 11:40 PM Erdem Derebaşoğlu <erdemderebasoglu at hotmail.com> wrote: Thanks for the response. How can I find out if an instruction uses a private memory access? Erdem From: vlknkls at gmail.com Date: Tue, 15 Sep 2015 14:38:16 +0000 Subject: Re: [llvm-dev]...

...etConstant(SrcOff, MVT::i64))); // Ops.push_back(SrcPtrInfo.getWithOffset(SrcOff)); Ops.push_back(DAG.getConstant(0, MVT::i64)); Loads[i] = DAG.getNode(AArch64::FakeLoad64, dl, VT, Ops); There seems to be something wrong with pointer information inside getNode() as llvm::MachinePointerInfo::getAddrSpace() asserts. I can't find an example of similar instructions to start with, are there any similar pseudoes already? Any help would be appreciated, even if someone could confirm that it should be possible to do and I'm just missing something. Thanks, Sergey

...nslation. Thats perhaps not the cleanest implementation, but it would work. > > I was going to suggest that an alternative is to pass this information in to the load/store instructions in the backend, but it looks like that information is already available. That is, MachinePointerInfo has a getAddrSpace() method. This could potentially allow you to optimize MachineInstrs using the same knowledge you have here, e.g., constness for addrspace(3) in MachineLICM. From here: http://llvm.org/docs/LangRef.html#pointer-type "The semantics of non-zero address spaces are target-specific." My i...

I would like to convert a C file that uses OpenMP library to X86 code with a condition: I want to insert a NOP before each instruction that does a private memory access.I have written an optimization pass that inserts an inline assembly call (NOP) but it is applied at IR level, and I cannot determine where to insert it. How can I use LLVM to add NOPs accordingly? Thanks. --------------

Have not gotten much further on this, I can so far only use one memory with (for example) def LDr1 : F1< (outs GenRegs:$dst), (ins GenRegs:$addr), "ld*0* $dst, ($addr)", [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>; and def LDrr : F1< (outs GenRegs:$dst), (ins MEMrr:$addr), "ld*0* $dst, ($addr)",

Can you send the IR you are using? Volkan On Thu, Oct 8, 2015 at 6:28 AM Erdem Derebaşoğlu < erdemderebasoglu at hotmail.com> wrote: > Thanks. I enabled my pass. I have one resolved issue though: > MachineMemOperand::getAddrSpace() always returns zero. How can I use it to > distinguish private memory accesses? > > Erdem > > ------------------------------ > From: vlknkls at gmail.com > Date: Sun, 4 Oct 2015 01:51:29 +0000 > > Subject: Re: [llvm-dev] How to add NOP? > To: erdemderebasoglu at hotm...

Hello, My target has two data memories, each with its own load/store instructions but also has some instructions using both memories. I want to be able to access both memories in C-programs through the address space attribute. I have two ideas so far: Either: use two sets of addressing modes in InstrInfo.td: def ADDRrr_A : ComplexPattern<i16, 2, “SelectADDRrr_A", [], []>; def ADDRri :

> I don’t know if CUDA has aliasing address spaces, but that would also be > useful to consider. Something simple like this might work. Note i’m > using the examples from the clang discussion, that is "1 = opencl/cuda > global, 2 = opencl_local/cuda_shared, 3 = opencl/cuda constant" You are assuming that the target device has different physical address spaces (like, PTX

We'd like to be able to vary the latency of our load instructions based on what address space is being loaded from. I was thinking I could do this by overriding getOperandLatency in our target, but I'm wondering if the addrspace info is available when instructions are scheduled? For example, I have this in our llvm IR: %0 = load i32 addrspace(4)* @answer, align 4 store i32 %0, i32*

On Aug 7, 2013, at 2:07 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote: > On 08/07/2013 01:52 PM, Michele Scandale wrote: >> >> IMHO this information should be a plus that could be *safely* ignored when not necessary and used where it can provide an improvement in optimizations. This does not necessary mean the the middle-end (and the back-ends) must be aware of the