Displaying 3 results from an estimated 3 matches for "fixedstack14".
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2012 Jan 27
2
[LLVMdev] Double spills with Greedy regalloc
...mem:ST2[FixedStack12](align=1)
STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1)
STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1)
STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1)
STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1)
Each STDWPtrQRr is a spill instruction, but notice that it's spil...
2012 Jan 27
0
[LLVMdev] Double spills with Greedy regalloc
...](align=1)
> STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
> STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
> STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
> STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1)
> STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1)
> STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1)
> STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1)
>
> Each STDWPtrQRr is a spill instruction, but...
2011 Oct 21
0
[LLVMdev] Problems with live intervals and spilling when having sub registers?
...s I get the following intervals for %vreg64:
%vreg64 = [288d,304d:1)[304d,320d:0) 0 at 304d 1 at 288d
Later %vreg6 and %vreg64 are merged. The register allocator spills
%vreg6 (fi#14) and the resulting code is
%r0l<def> = mv_any16 65535
Store32FI %r0<kill>, <fi#14>; mem:ST4[FixedStack14] %r0h<def> = mv_any16
16383 %r1<def> = Load32FI <fi#14>; mem:LD4[FixedStack14]
So the whole %r0 register is spilled to the stack after only one half is
written, and then what is supposed to go into the other half is never
used. Instead the previously written value is reloaded...