Displaying 2 results from an estimated 2 matches for "fixedstack12".
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fixedstack1
2012 Jan 27
2
[LLVMdev] Double spills with Greedy regalloc
Hello,
I noticed the following interesting code sequence while compiling a piece
of code with the backend I'm developing. Probably this issue is for Jakob,
but anyways this is what I'm getting:
STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=...
2012 Jan 27
0
[LLVMdev] Double spills with Greedy regalloc
...Borja Ferrer wrote:
> Hello,
>
> I noticed the following interesting code sequence while compiling a piece of code with the backend I'm developing. Probably this issue is for Jakob, but anyways this is what I'm getting:
>
> STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
> STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
> STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
> STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
> STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[...