search for: fgr32

hi all I have a question about implementing a new instruction which does this function f(x) = x + ceilf (x) .x is a single float i have already added the instruction in my backend in the .td file def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fadd (f32 FGR32:$fs ),(f32 (ceilf FGR32:$fs))))] >; it makes and install correctly but when i ll try to write code to use this instruction there is no luck. Should i do something in ISelLowering.cpp or ISelDAGToDAG...

...is instruction is defined as follows: // Instructions that convert an FP value to 64-bit fixed point. let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in multiclass FFR1_L_M<bits<6> funct, string opstr> { def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>; def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>; } // Instructions that convert an FP value to 32-bit fixed point. multiclass FFR1_W_M<bits<6> funct, string opstr> { def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>; def _D32 : FFR...

...as follows: > > // Instructions that convert an FP value to 64-bit fixed point. > let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in > multiclass FFR1_L_M<bits<6> funct, string opstr> { > def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>; > def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>; > } > > // Instructions that convert an FP value to 32-bit fixed point. > multiclass FFR1_W_M<bits<6> funct, string opstr> { > def _S : FFR1<funct, 16, opstr, "w.s", FGR3...

Hi, > def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), > "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fadd (f32 FGR32:$fs ),(f32 > (ceilf FGR32:$fs))))] >; > > it makes and install correctly but when i ll try to write code to use this > instruction there is no luck. More details (including the .ll s...

Hi, > i ve uploaded .ll file Is that the C file that's at the end of your message? To produce a .ll file, you give clang the "-emit-llvm" option (and probably "-S"). Anyway, what I see in the C you posted is that Clang is using constant folding to avoid doing any of the operations you've requested. A better C file test would be: float foo(float d) { return d -

>I'm also a little worried that your pattern has fadd, but your C >source has a subtraction. :S i wrote it wrong the true implementation is def SUBCEIL_S : FFR<0x11, 0x3, 16, (outs FGR32:$fd), (ins FGR32:$fs), "frac.s\t$fd, $fs", [(set (f32 FGR32:$fd), (fsub (f32 FGR32:$fs ),(f32 (ceilf FGR32:$fs))))] >; I use some C,C++ code to test my backend. i use clang with those argument -m32 -emit-llvm -S -target mipsel-linux-gnu -I.. and i have tried to add this in...

Hi and thanks for answering llc works fine just does not selecting my instruction i ve uploaded .ll file how can i include this attribute "readonly" so i can see if changes the generated assembly? my code is very simple int main (){ float d, d1 ; d= 12.3; d1 = d - ceilf(d); return 0; } -- View this message in context:

...as to add the following two lines next to the square root lines in the code (FPU and sqrt are enabled in llc): def FSQRT : ArithF2<0x16, 0x300, "fsqrt ", IIAlu>; def FNEG : ArithF2<0x16, 0x300, "fneg ", IIAlu>; // added for fneg and def : Pat<(fsqrt FGR32:$V), (FSQRT FGR32:$V)>; def : Pat<(fneg FGR32:$V), (FNEG FGR32:$V)>; // added for fneg Does anyone know what common causes of "UNREACHABLE executed!" messages are and what this message in particular means? The full error message is the following: UNREACHABLE executed! 0 llc...

Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>

Hello, About a month ago, I submitted a set of patches for review on llvm-commit. The most controversial of the patches, http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20150622/d104ea7 1/attachment-0009.obj deals with the fact that before ARMv8, the rGPR RegClass in Thumb encodings didn't include SP; but from ARMv8 onwards, it does include it. RegClass membership is