Displaying 5 results from an estimated 5 matches for "fa_roff1".
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fa_roff0
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...' is generated by LiveIntervalAnalysis, but I don't understand why it is generated and how to avoid this counterproductive optimization.
TIA, Dominique Torette.
# *** IR Dump After MachineFunction Printer ***:
# Machine code for function addproddivConst: Post SSA
Function Live Ins: %FA_ROFF1 in %vreg0
0B BB#0: derived from LLVM BB %entry
Live Ins: %FA_ROFF1
16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0
32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2
48B %vreg3<def> = FMUL_A_oo %vreg0,...
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
...egister class accepts the v2f32 type, but for others addressing mode context this register should be FPUabOffsetClass.
Is there a mechanism, an option to inforce/control the RegisterClass of registers defined by IMPLICIT_DEF ?
# Machine code for function vector2floatMulSum: SSA
Function Live Ins: %FA_ROFF1 in %vreg0, %FA_ROFF2 in %vreg1
BB#0: derived from LLVM BB %entry
Live Ins: %FA_ROFF1 %FA_ROFF2
%vreg1<def> = COPY %FA_ROFF2; FPUabOffsetClass:%vreg1
%vreg0<def> = COPY %FA_ROFF1; FPUabOffsetClass:%vreg0
%vreg3<def> = MOVSUTO_A_iSLo 1084227584, %RSPA<...
2018 Apr 03
1
Mapping virtual registers to physical registers
...function input parameters to machine specific registers.
My solution I found is based to the RegInfo.setSimpleHint() API.
Here is the body of the parameters loop of TargetLowering::LowerFormalArguments
VReg = RegInfo.createVirtualRegister(RC);
RegInfo.setSimpleHint(VReg,CLP::FA_ROFF1+i);
RegInfo.addLiveIn(CLP::FA_ROFF1+i, VReg);
Load = DAG.getCopyFromReg(Chain, Loc, VReg, ValVT.getSimpleVT().SimpleTy);
Thanks again for your support, Dominique T.
-----Original Message-----
From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Krzysztof Parzysz...
2018 Apr 02
0
Mapping virtual registers to physical registers
Hi Dominique,
From your description it is not really clear what you are trying to do
here. It may be the case that the goal you are trying to accomplish can
be better reached using a different approach.
In general, optimizations don't try to assign physical registers, that's
done by the register allocation passes. There are some cases when
target-specific passes use physical
2018 Mar 29
4
Mapping virtual registers to physical registers
Hi,
In the context of MachineCode custom inserter, I'm trying to enforce the mapping of virtual register to a physical one.
According to the documentation https://llvm.org/docs/CodeGenerator.html#mapping-virtual-registers-to-physical-registers
There are two ways: the direct one and the indirect ones. The indirect ones refer VirtRegMap class that I've never found. So I tried the direct