Displaying 5 results from an estimated 5 matches for "f32mem".
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i32mem
2013 May 20
2
[LLVMdev] VCOMISS instruction in X86
Hi,
I'm looking at scalar and packed instructions in X86.
The instruction VCOMISS is scalar. May I remove SSEPackedSingle/SSEPackedDouble domain from it?
defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
"ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
"ucomisd", SSEPackedDouble>, TB, OpSize, VEX,...
2009 Feb 10
0
[LLVMdev] Multiclass patterns
...eStr, "ss\t{$src2, $dst|$dst, $src2}"),
[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
let isCommutable = Commutable;
}
// Scalar operation, reg+mem.
def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
(ins FR32:$src1, f32mem:$src2),
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
[(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
// etc.
}
}
// Arithmetic instructions
defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss,...
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Bill,
Sorry if I wasn't clear enough. I wasn't referring to multiclass's that
define other classes, but with using patterns inside of a multiclass to
reduce redundant code.
For example:
multiclass IntSubtract<SDNode node>
{
def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
(ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
def _i32 : Pat<(sub
2009 May 15
1
[LLVMdev] RFC: More AVX Experience
...SRC1CLASS;
def SRC2CLASS;
def ADDRCLASS;
def INTRINSIC;
def TYPE;
def INTTYPE;
def MEMOP;
// TYPE - The data type (f32 for SS, f64 for SD, etc.)
// SRCREGCLASS - The source register class (VR128, FR32, etc.)
// DSTREGCLASS - The destination register class
// MEMCLASS - The memory classe (f32mem, f64mem, etc.)
// SRC1CLASS - The first source object class (register or memory, depending)
// SRC2CLASS - The second source object class (register or memory,
depending)
// DSTCLASS - The destination object class (register or memory, depending)
// ADDRCLASS - Either 'addr' or REGC...
2009 Apr 30
6
[LLVMdev] RFC: AVX Pattern Specification [LONG]
...eStr, "ss\t{$src2, $dst|$dst, $src2}"),
[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
let isCommutable = Commutable;
}
// Scalar operation, reg+mem.
def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
(ins FR32:$src1, f32mem:$src2),
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
[(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
// Vector operation, reg+reg.
def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),...