search for: i32mem

Hello, I m working towards backend. Here i need to define vector load and stores for 64 i32 elements. so in x86instrinfo.td i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))], IIC_MOV_MEM>, EVEX; def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst, VR2048:$src),...

Hi, All, I want to add one intrinsic function for my particular backend. Let's say the intrinsic function is named "foo" which takes two i32 inputs and has one i32 output. First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in /include/llvm/IR/Intrinsics.td. Then, in my target/InstrInfo.td, I'm supposed

Hi, in X86InstrArithmetic.td, we have LEA16r defined as: def LEA16r : I<0x8D, MRMSrcMem, (outs GR16:$dst), (ins i32mem:$src), "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize16; Please correct me if I am wrong, but I think "ins i32mem" should be "ins i16mem" because this is about 16bit register? So is this a bug? Thanks, Jun -------------- next part...

...[(set GR8:$dst, (load addr:$src))]>; def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", [(set GR16:$dst, (load addr:$src))]>, OpSize; def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", [(set GR32:$dst, (load addr:$src))]>; For my target processor, only the types of operands (e.g. rm) are really important. The size is encoded into the opcode, but otherwise it does not affect anything except for...

...nually > inside the code or using TableGen mechanism. For the latter, you should > define a pseudo-instruction that match your > intrinsic-translated-into-dag-node. The pseudo-instruction definition > should look like this: > > let isPseudo = 1 in { > def FOO : PseudoI<(outs i32mem:$dst), (ins i32mem:$src1, i32mem:$src2, ), > [(set i32mem:$dst, (int_foo i32mem:$src1, i32mem:$src2))]>; > } > > First, you should always set isPeudo to 1 if it is a pseudo-instruction. > Then, if it has some side effect, you should define them. For example, set > Defs = [EFLAG...

On Wednesday 10 July 2013 22:18:23 Jevin Sweval wrote: > http://www.cs.fsu.edu/~baker/devices/lxr/http/source/linux/arch/x86/include/ > asm/bitops.h#L68 > > Here is one example that I found. Are the inline assembly arguments > ambiguous in size? It would help us for sure to build the kernel and others. -- JS

Hi Jacob, thank you for your reply. Your suggestion works! But instead of using the Pat<>, I am using def MOVE_ADDR : MYInst<(outs Int32Regs:$dst), (ins i32mem:$a), "move $dst, $a;", [(set Int32Regs:$dst, (Wrapper tglobaladdr:$a))]>; I don't quite understand what the semantics of Pat in general. Could you please explain what def : Pat<(BfinWrapper (i32 tglobaladdr:$addr)), (LOAD32i...

...(set GR8:$dst, (load addr:$src))]>; > def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), > "mov{w} {$src, $dst|$dst, $src}", > [(set GR16:$dst, (load addr:$src))]>, OpSize; > def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), > "mov{l} {$src, $dst|$dst, $src}", > [(set GR32:$dst, (load addr:$src))]>; We must do this, because they perform different operations. Specifically, the loads all read a different number of bytes (1/2/4). > For my target processor, onl...

...ction to the X86 back end. xadd r/m32, r32 exchanges r/m32 and r32, and loads the sum into r/m32. I'm interested in the case where the destination operand is a memory location. I've added the following entry to X86InstrInfo.td: def XADD32mr : I<0x87, MRMDestMem, (ops i32mem:$src1, R32:$src2), "xadd{l} {$src1|$src2}, {$src2|$src1}">; The xadd is emitted for the intrinsic function: call int (<integer type>*, <integer type>)* %llvm.atomic_fetch_add_store(<integer type>* <pointer>,...

Hello! Can someone please tell me if is there an API (or some other way) to query MCInstrDesc to find out the type of its memory operands? As an example, consider the following description of MOV32mr (from X86InstrInfo.td) def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "mov{l}\t{$src, $dst|$dst, $src}", [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; or that of MOVSX64rm (from X86InstrExtension.td) def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),...

llvm/lib/Target/X86/X86InstrInfo.td: class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { .... dag OperandList = ops; string AsmString = AsmStr; } def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}">; I cannot find any document on initializing the 'dag' type variable, and I cannot understand the syntax of "asmstring" either. how does the x86 asmwrite interpret the "AsmString" ?

...uts), (ins i16mem:$dst, GR16:$src), +def MOV16mr : I<0x89, MRMDestMem, (outs i16mem:$dst), (ins GR16:$src), "mov{w}\t{$src, $dst|$dst, $src}", [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150324/4e58d04d/attachment.html>

...stRC:$dst, (OpNode SrcRC:$src))]>; def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>; } let isAsmParserOnly = 0 in { defm SInt_VCVTSI2SD : sse12_vcvt_avx_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32, "cvtsi2sd\t{$src, $dst, $dst|$dst, $dst, $src}">, XD, VEX; ... } let isAsmParserOnly = 1 in { defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD, VEX_...

On Tue, Jun 24, 2014 at 4:03 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Jun, > > On 24 June 2014 08:08, Jun Koi <junkoi2004 at gmail.com> wrote: > > def LEA16r : I<0x8D, MRMSrcMem, > > (outs GR16:$dst), (ins i32mem:$src), > > "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, > > OpSize16; > > > > > > Please correct me if I am wrong, but I think "ins i32mem" should be "ins > > i16mem" because this is about 16bit register?...

...r/m32, r32 > exchanges r/m32 and r32, and loads the sum into r/m32. I'm > interested in the case where the destination operand is a > memory location. > > I've added the following entry to X86InstrInfo.td: > def XADD32mr : I<0x87, MRMDestMem, > (ops i32mem:$src1, R32:$src2), This looks fine. > "xadd{l} {$src1|$src2}, {$src2|$src1}">; I haven't checked this, but it's probably fine. > The xadd is emitted for the intrinsic function: > call int (<integer type>*, <integer type>)* > %llvm.ato...

...u wrote: > llvm/lib/Target/X86/X86InstrInfo.td: > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > AsmStr> : Instruction { > .... > dag OperandList = ops; > string AsmString = AsmStr; > } > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > "mov{l} {$src, $dst|$dst, $src}">; > > I cannot find any document on initializing the 'dag' type variable, > and I cannot understand the syntax of "asmstring" either. The DAG operator is just a nested set of parens,...

...trInfo.td: > > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > > AsmStr> : Instruction { > > .... > > dag OperandList = ops; > > string AsmString = AsmStr; > > } > > > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > > "mov{l} {$src, $dst|$dst, $src}">; > > > > I cannot find any document on initializing the 'dag' type variable, > > and I cannot understand the syntax of "asmstring" either. > > The DAG operator i...

...hanges r/m32 and r32, and loads the sum into r/m32. I'm >>interested in the case where the destination operand is a >>memory location. >> >>I've added the following entry to X86InstrInfo.td: >>def XADD32mr : I<0x87, MRMDestMem, >> (ops i32mem:$src1, R32:$src2), > > > This looks fine. > > >> "xadd{l} {$src1|$src2}, {$src2|$src1}">; > > > I haven't checked this, but it's probably fine. > > >>The xadd is emitted for the intrinsic function: >>call in...

...load addr:$src))]>; >> def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), >> "mov{w} {$src, $dst|$dst, $src}", >> [(set GR16:$dst, (load addr:$src))]>, OpSize; >> def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), >> "mov{l} {$src, $dst|$dst, $src}", >> [(set GR32:$dst, (load addr:$src))]>; > > We must do this, because they perform different operations. Specifically, > the loads all read a different number of bytes (1/2/4). OK. &gt...

...644 > --- a/lib/Target/X86/X86InstrInfo.td > +++ b/lib/Target/X86/X86InstrInfo.td > @@ -1971,6 +1971,10 @@ def : InstAlias<"aam", (AAM8i8 10)>; > // Disambiguate the mem/imm form of bt-without-a-suffix as btl. > def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>; > > +// Disambiguate btr and bts, just like GNU as. > +def : InstAlias<"btr $imm, $mem", (BT16mi8 i16mem:$mem, i16i8imm:$imm)>; > +def : InstAlias<"bts $imm, $mem", (BT16mi8 i16mem:$mem, i16i8imm:$imm)>; > + > // clr alias...