search for: f128mem

...ISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX, VEX_LIG; let Pattern = []<dag> in { defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load, "comiss", SSEPackedSingle>, TB, VEX, VEX_LIG; defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load, "comisd", SSEPackedDouble>, TB, O...

...outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc), > asm_alt, [], itins.rm, d>, > Sched<[WriteFAddLd, ReadAfterLd]>; > } > } > > > let Constraints = "$src1 = $dst" in > { > defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, > int_x86_sse_cmp_ps, > "cmp${cc}ps\t{$src2, $dst|$dst, > $src2}", > "cmpps\t{$cc, $src2, $dst|$dst, $src2, > $cc}", > SSEPackedSingle, SSE_ALU_F32P>, > PS; > defm CMPPD : sse12_cmp_packed&lt...

On Feb 15, 2010, at 1:04 PM, David Greene wrote: >> FWIW, this is because you broke the encoding of an instruction in your >> patch. This is incorrect: >> >> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, >> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", >> + [(alignednontemporalstore (v2f64 VR128:$src), >> addr:$dst)]>; >> >> Please don't check in patches when you know that they break testcases. > &g...

hi, some instructions mismatch between assembler & disassembler, like below. it seems this happens with all SSECC related instructions? thanks, Jun $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding .text cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] $

...>> for a while, maybe someone should mark it XFAIL? > > It passed for me until you applied your patch, I reverted it in r96265. FWIW, this is because you broke the encoding of an instruction in your patch. This is incorrect: +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", + [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>; Please don't check in patches when you know that they break testcases. -Chris

...vm_v2f64_ty], [IntrNoMem]>; This matches the signature of the GCC intrinsic. The fact that the GCC intrinsic has a type mismatch on the input (vector rather than scalar) is strange, but ok, we'll run with it. Until this: def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem: $src), "cvtsd2si\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (int_x86_sse2_cvtsd2si (load addr:$src)))]>; Er, this makes us load a 128-bit quantity, which is almost certainly not what we want...

...s Lattner wrote: >> On Feb 15, 2010, at 1:04 PM, David Greene wrote: >>>> FWIW, this is because you broke the encoding of an instruction in your >>>> patch. This is incorrect: >>>> >>>> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, >>>> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", >>>> + [(alignednontemporalstore (v2f64 VR128:$src), >>>> addr:$dst)]>; >>>> >>>> Please don't check in patches when you...

...010 15:08:22 Chris Lattner wrote: > On Feb 15, 2010, at 1:04 PM, David Greene wrote: > >> FWIW, this is because you broke the encoding of an instruction in your > >> patch. This is incorrect: > >> > >> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, > >> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", > >> + [(alignednontemporalstore (v2f64 VR128:$src), > >> addr:$dst)]>; > >> > >> Please don't check in patches when you know that they b...

...eone should mark it XFAIL? > > > > It passed for me until you applied your patch, I reverted it in r96265. > > FWIW, this is because you broke the encoding of an instruction in your > patch. This is incorrect: > > +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, > VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", > + [(alignednontemporalstore (v2f64 VR128:$src), > addr:$dst)]>; > > Please don't check in patches when you know that they break testcases. I certainly didn't know...

...tions in .td files: one through the traditional shuffle operators like unpckl and shufp and another through these special X86* operators. This is reflected in X86InstrSSE.td: "Traditional": defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32, VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}", SSEPackedSingle>, VEX_4V; "New-style": def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))), (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]&gt...

In ToT, LowerVECTOR_SHUFFLE for x86 has this code: if (X86::isUNPCKLMask(SVOp)) getTargetShuffleNode(getUNPCKLOpcode(VT) dl, VT, V1, V2, DAG); why would this not be: if (X86::isUNPCKLMask(SVOp)) return SVOp; I'm trying to add support for VUNPCKL and am getting into trouble because the existing code ends up creating: VUNPCKLPS load load which is badness come selection

...es the signature of the GCC intrinsic. The fact that the > GCC > intrinsic has a type mismatch on the input (vector rather than scalar) > is strange, but ok, we'll run with it. > > Until this: > > def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins > f128mem: > $src), > "cvtsd2si\t{$src, $dst|$dst, $src}", > [(set GR32:$dst, (int_x86_sse2_cvtsd2si > (load addr:$src)))]>; > > Er, this makes us load a 128-bit quantity, which is almost...

...t;> On Feb 15, 2010, at 1:04 PM, David Greene wrote: > >>>> FWIW, this is because you broke the encoding of an instruction in your > >>>> patch. This is incorrect: > >>>> > >>>> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, > >>>> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", > >>>> + [(alignednontemporalstore (v2f64 VR128:$src), > >>>> addr:$dst)]>; > >>>> > >>>> Please don't ch...

...!strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst, $src2}"), [(set VR128:$dst, v2i64 (OpNode VR128:$src1, VR128: $src2))]>; // Bitconverted vector operation def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)), (memopv2i64 addr:$src2)))]>; // ... } defm AND : ... defm OR : ... I suspect we cou...

Hi all, I'm trying to simulate an extended x86 architecture on gem5 with several new instructions. My hardware setup is done and now I'd like llvm to accept the existence of the new instruction passed in inline assembly and output the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and I would like the instruction to have the same operands and return values as CVTPS2PI

On Fri, Jun 5, 2009 at 8:51 AM, David Greene<dag at cray.com> wrote: > def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem: > $src), >                         "cvtsd2si\t{$src, $dst|$dst, $src}", >                         [(set GR32:$dst, (int_x86_sse2_cvtsd2si >                                           (load addr:$src)))]>; > > Er, this makes us load a 128-bit quantity, which is almost...

On Monday 15 February 2010 11:54:25 Óscar Fuentes wrote: > David Greene <dag at cray.com> writes: > > Sorry, I botched a commit and broke the build. I've just committed a > > fix. > > > > So expect to see some buildbot churning. > > Don't hurry. A buildbot already decided that I am the only culprit of > the breakage. :-/ Hmm...given that

On Feb 15, 2010, at 10:00 AM, David Greene wrote: > On Monday 15 February 2010 11:54:25 Óscar Fuentes wrote: >> David Greene <dag at cray.com> writes: >>> Sorry, I botched a commit and broke the build. I've just committed a >>> fix. >>> >>> So expect to see some buildbot churning. >> >> Don't hurry. A buildbot already

...s Lattner wrote: >> On Feb 15, 2010, at 1:04 PM, David Greene wrote: >>>> FWIW, this is because you broke the encoding of an instruction in your >>>> patch. This is incorrect: >>>> >>>> +def MOVNTDQ_64mr : PSI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, >>>> VR128:$src), + "movntdq\t{$src, $dst|$dst, $src}", >>>> + [(alignednontemporalstore (v2f64 VR128:$src), >>>> addr:$dst)]>; >>>> >>>> Please don't check in patches when you...

...ps"\t{$src2, $dst|$dst, > $src2}"), > [(set VR128:$dst, v2i64 (OpNode VR128:$src1, > VR128: > $src2))]>; > > // Bitconverted vector operation > def PSrm : PSI<opc, MRMSrcMem, > (outs VR128:$dst), (ins VR128:$src1, f128mem: > $src2), > !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, > $src2}"), > [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 > VR128:$src1)), > (memopv2i64 addr:$src2)))]>; > // ... > } >...